[llvm-bugs] [Bug 49549] Expected an XLenVT or scalable vector types at this stage assert when building SIMD code on RISCV

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=49549

simonas+llvm.org at kazlauskas.me changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|NEW                         |RESOLVED

--- Comment #3 from simonas+llvm.org at kazlauskas.me ---
Yeah, looks like it works now.

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