[llvm-bugs] [Bug 51318] New: [SchedModel] Missing ReadAdvance on the implicit use of EFLAGS in RM and MR variants of ADC/SBB

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=51318

            Bug ID: 51318
           Summary: [SchedModel] Missing ReadAdvance on the implicit use
                    of EFLAGS in RM and MR variants of ADC/SBB
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: andrea.dibiagio at gmail.com
                CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org,
                    llvm-dev at redking.me.uk, pengfei.wang at intel.com,
                    spatel+llvm at rotateright.com

Example:

```
adc %rax, (%rsp)
```

> llvm-mca -mcpu=btver2 -timeline -iterations=2

The timeline view reports this:

```
Timeline view:
                    01234
Index     0123456789     

[0,0]     DeeeeeeER .   .   adcq        %rax, (%rsp)
[1,0]     D======eeeeeeER   adcq        %rax, (%rsp)
```

The load from RSP can start execution before RAX becomes available.
So, most of the load latency can be effectively hidden.

It turns out that we do correctly set a ReadAdvance for the read of RAX.
However, we forgot to do the same for the implicit read EFLAGS.

For reference, this is how it works for normal ADDs (i.e. no carry dependency).
For ADC, the timeline should be identical.

```
Timeline view:
Index     012345678

[0,0]     DeeeeeER.   addl      4(%rsp), %eax
[0,1]     D=eeeeeER   addl      (%rsp), %eax
```

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