[llvm-bugs] [Bug 51317] New: `and 0xff` on load of 1 byte

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=51317

            Bug ID: 51317
           Summary: `and 0xff` on load of 1 byte
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: kutdanila at yandex.ru
                CC: arnaud.degrandmaison at arm.com,
                    llvm-bugs at lists.llvm.org, smithp352 at googlemail.com,
                    Ties.Stuij at arm.com

Minimal example https://gcc.godbolt.org/z/z8GrK6v95



DecompressBranchless
        ldrb    w8, [x0], #1
.LBB0_1:                                // =>This Inner Loop Header: Depth=1
        and     x9, x8, #0xff           // Redundant!!!!!!!!!
        ldrh    w11, [x5, x9, lsl #1]
        ubfx    x10, x8, #2, #6
        ands    x8, x8, #0x3
        csinc   x8, x8, x10, ne
        add     x10, x2, x11
        add     x9, x0, x8
        add     x11, x3, x10
        ldrb    w8, [x9], #1
        csel    x11, x0, x11, eq
        ldrb    w11, [x11]
        cmp     x9, x1
        strb    w11, [x3, x2]
        b.hs    .LBB0_3
        cmp     x10, x4
        mov     x0, x9
        mov     x2, x10
        b.lt    .LBB0_1
.LBB0_3:
        ret


After adding `asm("" ::"r"(tag));`, and is removed


DecompressBranchlessBetter
        ldrb    w8, [x0], #1
.LBB1_1:                                // =>This Inner Loop Header: Depth=1
        ldrh    w10, [x5, x8, lsl #1]
        lsr     x9, x8, #2
        ands    x8, x8, #0x3
        csinc   x8, x8, x9, ne
        add     x10, x2, x10
        add     x9, x0, x8
        add     x11, x3, x10
        ldrb    w8, [x9], #1
        csel    x11, x0, x11, eq
        ldrb    w11, [x11]
        cmp     x9, x1
        strb    w11, [x3, x2]
        b.hs    .LBB1_3
        cmp     x10, x4
        mov     x0, x9
        mov     x2, x10
        b.lt    .LBB1_1
.LBB1_3:
        ret

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