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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [SchedModel] Missing ReadAdvance on the implicit use of EFLAGS in RM and MR variants of ADC/SBB"
href="https://bugs.llvm.org/show_bug.cgi?id=51318">51318</a>
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<th>Summary</th>
<td>[SchedModel] Missing ReadAdvance on the implicit use of EFLAGS in RM and MR variants of ADC/SBB
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
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<th>Reporter</th>
<td>andrea.dibiagio@gmail.com
</td>
</tr>
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<th>CC</th>
<td>craig.topper@gmail.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, pengfei.wang@intel.com, spatel+llvm@rotateright.com
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<pre>Example:
```
adc %rax, (%rsp)
```
<span class="quote">> llvm-mca -mcpu=btver2 -timeline -iterations=2</span >
The timeline view reports this:
```
Timeline view:
01234
Index 0123456789
[0,0] DeeeeeeER . . adcq %rax, (%rsp)
[1,0] D======eeeeeeER adcq %rax, (%rsp)
```
The load from RSP can start execution before RAX becomes available.
So, most of the load latency can be effectively hidden.
It turns out that we do correctly set a ReadAdvance for the read of RAX.
However, we forgot to do the same for the implicit read EFLAGS.
For reference, this is how it works for normal ADDs (i.e. no carry dependency).
For ADC, the timeline should be identical.
```
Timeline view:
Index 012345678
[0,0] DeeeeeER. addl 4(%rsp), %eax
[0,1] D=eeeeeER addl (%rsp), %eax
```</pre>
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