[llvm-branch-commits] [llvm] [SelectionDAG] Handle constants in SimplifyMultipleUseDemandedBits (PR #224882)
Harrison Hao via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sun Sep 20 02:57:04 PDT 2026
https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/224882
>From 8b94ad3fbea0daa4cddd2a45e271738bc1cb986d Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Sun, 20 Sep 2026 11:57:39 +0800
Subject: [PATCH] [SelectionDAG] Handle constants in
SimplifyMultipleUseDemandedBits
Replace a non-zero constant with zero when none of its set bits are
demanded.
This allows users of `SimplifyMultipleUseDemandedBits` to eliminate
irrelevant constant bits while preserving the convention that a null
SDValue indicates no simplification.
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 6 ++
.../CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll | 9 +-
llvm/test/CodeGen/AMDGPU/rotate-add.ll | 4 +-
llvm/test/CodeGen/AMDGPU/rotl.ll | 83 +++++++++----------
llvm/test/CodeGen/AVR/issue-132203.ll | 4 -
llvm/test/CodeGen/Mips/rotate.ll | 2 +-
llvm/test/CodeGen/PowerPC/ppc-rotate-clear.ll | 7 +-
llvm/test/CodeGen/PowerPC/rotl-2.ll | 2 +-
llvm/test/CodeGen/SystemZ/shift-04.ll | 6 +-
llvm/test/CodeGen/SystemZ/shift-08.ll | 6 +-
10 files changed, 58 insertions(+), 71 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index b4e34c255a1e9..0dc5a63f54dfd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -766,6 +766,12 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
unsigned BitWidth = DemandedBits.getBitWidth();
KnownBits LHSKnown, RHSKnown;
switch (Op.getOpcode()) {
+ case ISD::Constant: {
+ const APInt &Value = Op->getAsAPIntVal();
+ if (!Value.isZero() && (Value & DemandedBits).isZero())
+ return DAG.getConstant(0, SDLoc(Op), VT);
+ break;
+ }
case ISD::BITCAST: {
if (VT.isScalableVector())
return SDValue();
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
index 380a28bf03229..b5c1eb267b6fc 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
@@ -78,23 +78,20 @@ define amdgpu_kernel void @test_mul_i24_zero_lhs(ptr addrspace(1) %out, i32 %src
define amdgpu_kernel void @test_mul_i24_zero_low24(ptr addrspace(1) %out, i32 %src) #1 {
; GCN-LABEL: test_mul_i24_zero_low24:
; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dword s6, s[4:5], 0xb
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GCN-NEXT: v_mov_b32_e32 v0, 0x1000000
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1
+; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mul_i32_i24_e32 v0, s6, v0
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm
;
; GFX12-LABEL: test_mul_i24_zero_low24:
; GFX12: ; %bb.0:
-; GFX12-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mul_i32_i24_e64 v1, 0x1000000, s2
-; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT: global_store_b32 v0, v0, s[0:1]
; GFX12-NEXT: s_endpgm
%val = call i32 @llvm.amdgcn.mul.i24(i32 %src, i32 16777216) #0
store i32 %val, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/rotate-add.ll b/llvm/test/CodeGen/AMDGPU/rotate-add.ll
index c1dcfc0ec15dd..47add1bfcfa7e 100644
--- a/llvm/test/CodeGen/AMDGPU/rotate-add.ll
+++ b/llvm/test/CodeGen/AMDGPU/rotate-add.ll
@@ -42,14 +42,14 @@ define i32 @test_rotl_var(i32 %x, i32 %y) {
; SI-LABEL: test_rotl_var:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v1
+; SI-NEXT: v_sub_i32_e32 v1, vcc, 0, v1
; SI-NEXT: v_alignbit_b32 v0, v0, v0, v1
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: test_rotl_var:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v1
+; VI-NEXT: v_sub_u32_e32 v1, vcc, 0, v1
; VI-NEXT: v_alignbit_b32 v0, v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
%shl = shl i32 %x, %y
diff --git a/llvm/test/CodeGen/AMDGPU/rotl.ll b/llvm/test/CodeGen/AMDGPU/rotl.ll
index c74d485767922..43f6e38aa1bc7 100644
--- a/llvm/test/CodeGen/AMDGPU/rotl.ll
+++ b/llvm/test/CodeGen/AMDGPU/rotl.ll
@@ -9,13 +9,12 @@
define amdgpu_kernel void @rotl_i32(ptr addrspace(1) %in, i32 %x, i32 %y) {
; R600-LABEL: rotl_i32:
; R600: ; %bb.0: ; %entry
-; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
-; R600-NEXT: SUB_INT * T0.W, literal.x, KC0[2].W,
-; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; R600-NEXT: SUB_INT * T0.W, 0.0, KC0[2].W,
; R600-NEXT: BIT_ALIGN_INT T0.X, KC0[2].Z, KC0[2].Z, PV.W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
@@ -27,7 +26,7 @@ define amdgpu_kernel void @rotl_i32(ptr addrspace(1) %in, i32 %x, i32 %y) {
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s0
-; SI-NEXT: s_sub_i32 s0, 32, s3
+; SI-NEXT: s_sub_i32 s0, 0, s3
; SI-NEXT: s_and_b32 s0, s0, 31
; SI-NEXT: s_mov_b32 s3, s2
; SI-NEXT: s_mov_b32 s5, s1
@@ -40,7 +39,7 @@ define amdgpu_kernel void @rotl_i32(ptr addrspace(1) %in, i32 %x, i32 %y) {
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_sub_i32 s4, 32, s3
+; GFX8-NEXT: s_sub_i32 s4, 0, s3
; GFX8-NEXT: s_mov_b32 s3, s2
; GFX8-NEXT: s_and_b32 s4, s4, 31
; GFX8-NEXT: s_lshr_b64 s[2:3], s[2:3], s4
@@ -55,7 +54,7 @@ define amdgpu_kernel void @rotl_i32(ptr addrspace(1) %in, i32 %x, i32 %y) {
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_sub_i32 s3, 32, s3
+; GFX10-NEXT: s_sub_i32 s3, 0, s3
; GFX10-NEXT: s_and_b32 s4, s3, 31
; GFX10-NEXT: s_mov_b32 s3, s2
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s4
@@ -67,7 +66,7 @@ define amdgpu_kernel void @rotl_i32(ptr addrspace(1) %in, i32 %x, i32 %y) {
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_sub_i32 s3, 32, s3
+; GFX11-NEXT: s_sub_i32 s3, 0, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s4, s3, 31
; GFX11-NEXT: s_mov_b32 s3, s2
@@ -88,16 +87,14 @@ entry:
define amdgpu_kernel void @rotl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {
; R600-LABEL: rotl_v2i32:
; R600: ; %bb.0: ; %entry
-; R600-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
-; R600-NEXT: SUB_INT * T0.W, literal.x, KC0[3].Z,
-; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; R600-NEXT: SUB_INT * T0.W, 0.0, KC0[3].Z,
; R600-NEXT: BIT_ALIGN_INT T0.Y, KC0[3].X, KC0[3].X, PV.W,
-; R600-NEXT: SUB_INT * T0.W, literal.x, KC0[3].Y,
-; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; R600-NEXT: SUB_INT * T0.W, 0.0, KC0[3].Y,
; R600-NEXT: BIT_ALIGN_INT T0.X, KC0[2].W, KC0[2].W, PV.W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
@@ -109,8 +106,8 @@ define amdgpu_kernel void @rotl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_sub_i32 s8, 32, s2
-; SI-NEXT: s_sub_i32 s2, 32, s3
+; SI-NEXT: s_sub_i32 s8, 0, s2
+; SI-NEXT: s_sub_i32 s2, 0, s3
; SI-NEXT: s_and_b32 s9, s2, 31
; SI-NEXT: s_mov_b32 s2, s1
; SI-NEXT: s_mov_b32 s3, s1
@@ -128,8 +125,8 @@ define amdgpu_kernel void @rotl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_sub_i32 s7, 32, s3
-; GFX8-NEXT: s_sub_i32 s6, 32, s2
+; GFX8-NEXT: s_sub_i32 s7, 0, s3
+; GFX8-NEXT: s_sub_i32 s6, 0, s2
; GFX8-NEXT: s_mov_b32 s2, s1
; GFX8-NEXT: s_mov_b32 s3, s1
; GFX8-NEXT: s_and_b32 s1, s7, 31
@@ -151,8 +148,8 @@ define amdgpu_kernel void @rotl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_sub_i32 s4, 32, s2
-; GFX10-NEXT: s_sub_i32 s5, 32, s3
+; GFX10-NEXT: s_sub_i32 s4, 0, s2
+; GFX10-NEXT: s_sub_i32 s5, 0, s3
; GFX10-NEXT: s_mov_b32 s2, s1
; GFX10-NEXT: s_mov_b32 s3, s1
; GFX10-NEXT: s_mov_b32 s1, s0
@@ -171,8 +168,8 @@ define amdgpu_kernel void @rotl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_sub_i32 s6, 32, s2
-; GFX11-NEXT: s_sub_i32 s7, 32, s3
+; GFX11-NEXT: s_sub_i32 s6, 0, s2
+; GFX11-NEXT: s_sub_i32 s7, 0, s3
; GFX11-NEXT: s_mov_b32 s2, s1
; GFX11-NEXT: s_mov_b32 s3, s1
; GFX11-NEXT: s_mov_b32 s1, s0
@@ -197,22 +194,18 @@ entry:
define amdgpu_kernel void @rotl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {
; R600-LABEL: rotl_v4i32:
; R600: ; %bb.0: ; %entry
-; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
-; R600-NEXT: SUB_INT * T0.W, literal.x, KC0[5].X,
-; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; R600-NEXT: SUB_INT * T0.W, 0.0, KC0[5].X,
; R600-NEXT: BIT_ALIGN_INT T0.W, KC0[4].X, KC0[4].X, PV.W,
-; R600-NEXT: SUB_INT * T1.W, literal.x, KC0[4].W,
-; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; R600-NEXT: SUB_INT * T1.W, 0.0, KC0[4].W,
; R600-NEXT: BIT_ALIGN_INT T0.Z, KC0[3].W, KC0[3].W, PS,
-; R600-NEXT: SUB_INT * T1.W, literal.x, KC0[4].Z,
-; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; R600-NEXT: SUB_INT * T1.W, 0.0, KC0[4].Z,
; R600-NEXT: BIT_ALIGN_INT T0.Y, KC0[3].Z, KC0[3].Z, PV.W,
-; R600-NEXT: SUB_INT * T1.W, literal.x, KC0[4].Y,
-; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; R600-NEXT: SUB_INT * T1.W, 0.0, KC0[4].Y,
; R600-NEXT: BIT_ALIGN_INT T0.X, KC0[3].Y, KC0[3].Y, PV.W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
@@ -224,16 +217,16 @@ define amdgpu_kernel void @rotl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_sub_i32 s4, 32, s15
+; SI-NEXT: s_sub_i32 s4, 0, s15
; SI-NEXT: s_and_b32 s7, s4, 31
; SI-NEXT: s_mov_b32 s4, s11
; SI-NEXT: s_mov_b32 s5, s11
-; SI-NEXT: s_sub_i32 s6, 32, s14
+; SI-NEXT: s_sub_i32 s6, 0, s14
; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], s7
-; SI-NEXT: s_sub_i32 s13, 32, s13
+; SI-NEXT: s_sub_i32 s13, 0, s13
; SI-NEXT: s_and_b32 s5, s6, 31
; SI-NEXT: s_mov_b32 s11, s10
-; SI-NEXT: s_sub_i32 s12, 32, s12
+; SI-NEXT: s_sub_i32 s12, 0, s12
; SI-NEXT: s_lshr_b64 s[6:7], s[10:11], s5
; SI-NEXT: s_and_b32 s5, s13, 31
; SI-NEXT: s_mov_b32 s10, s9
@@ -254,16 +247,16 @@ define amdgpu_kernel void @rotl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_sub_i32 s2, 32, s15
+; GFX8-NEXT: s_sub_i32 s2, 0, s15
; GFX8-NEXT: s_and_b32 s5, s2, 31
; GFX8-NEXT: s_mov_b32 s2, s11
; GFX8-NEXT: s_mov_b32 s3, s11
-; GFX8-NEXT: s_sub_i32 s4, 32, s14
+; GFX8-NEXT: s_sub_i32 s4, 0, s14
; GFX8-NEXT: s_lshr_b64 s[2:3], s[2:3], s5
-; GFX8-NEXT: s_sub_i32 s6, 32, s13
+; GFX8-NEXT: s_sub_i32 s6, 0, s13
; GFX8-NEXT: s_and_b32 s3, s4, 31
; GFX8-NEXT: s_mov_b32 s11, s10
-; GFX8-NEXT: s_sub_i32 s12, 32, s12
+; GFX8-NEXT: s_sub_i32 s12, 0, s12
; GFX8-NEXT: s_lshr_b64 s[4:5], s[10:11], s3
; GFX8-NEXT: s_and_b32 s3, s6, 31
; GFX8-NEXT: s_mov_b32 s6, s9
@@ -288,10 +281,10 @@ define amdgpu_kernel void @rotl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_sub_i32 s6, 32, s12
-; GFX10-NEXT: s_sub_i32 s7, 32, s13
-; GFX10-NEXT: s_sub_i32 s12, 32, s14
-; GFX10-NEXT: s_sub_i32 s13, 32, s15
+; GFX10-NEXT: s_sub_i32 s6, 0, s12
+; GFX10-NEXT: s_sub_i32 s7, 0, s13
+; GFX10-NEXT: s_sub_i32 s12, 0, s14
+; GFX10-NEXT: s_sub_i32 s13, 0, s15
; GFX10-NEXT: s_mov_b32 s2, s11
; GFX10-NEXT: s_mov_b32 s3, s11
; GFX10-NEXT: s_mov_b32 s11, s10
@@ -319,10 +312,10 @@ define amdgpu_kernel void @rotl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i
; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_sub_i32 s6, 32, s12
-; GFX11-NEXT: s_sub_i32 s7, 32, s13
-; GFX11-NEXT: s_sub_i32 s12, 32, s14
-; GFX11-NEXT: s_sub_i32 s13, 32, s15
+; GFX11-NEXT: s_sub_i32 s6, 0, s12
+; GFX11-NEXT: s_sub_i32 s7, 0, s13
+; GFX11-NEXT: s_sub_i32 s12, 0, s14
+; GFX11-NEXT: s_sub_i32 s13, 0, s15
; GFX11-NEXT: s_mov_b32 s2, s11
; GFX11-NEXT: s_mov_b32 s3, s11
; GFX11-NEXT: s_mov_b32 s11, s10
diff --git a/llvm/test/CodeGen/AVR/issue-132203.ll b/llvm/test/CodeGen/AVR/issue-132203.ll
index 4576a580185ff..580040dfd0df0 100644
--- a/llvm/test/CodeGen/AVR/issue-132203.ll
+++ b/llvm/test/CodeGen/AVR/issue-132203.ll
@@ -45,8 +45,6 @@ define i16 @fooe(i8 %a) {
; MOVW-LABEL: fooe:
; MOVW: ; %bb.0:
; MOVW-NEXT: clr r25
-; MOVW-NEXT: subi r24, 0
-; MOVW-NEXT: sbci r25, 1
; MOVW-NEXT: andi r24, 1
; MOVW-NEXT: andi r25, 0
; MOVW-NEXT: ret
@@ -54,8 +52,6 @@ define i16 @fooe(i8 %a) {
; NOMOVW-LABEL: fooe:
; NOMOVW: ; %bb.0:
; NOMOVW-NEXT: clr r25
-; NOMOVW-NEXT: subi r24, 0
-; NOMOVW-NEXT: sbci r25, 1
; NOMOVW-NEXT: andi r24, 1
; NOMOVW-NEXT: andi r25, 0
; NOMOVW-NEXT: ret
diff --git a/llvm/test/CodeGen/Mips/rotate.ll b/llvm/test/CodeGen/Mips/rotate.ll
index 6fe6639285caf..8d523ec1f26be 100644
--- a/llvm/test/CodeGen/Mips/rotate.ll
+++ b/llvm/test/CodeGen/Mips/rotate.ll
@@ -7,7 +7,7 @@
; CHECK: rotrv $2, $4
; mips16: .ent rot0
-; MM32: li16 $2, 32
+; MM32: li16 $2, 0
; MM32: subu16 $2, $2, $5
; MM32: rotrv $2, $4, $2
define i32 @rot0(i32 %a, i32 %b) nounwind readnone {
diff --git a/llvm/test/CodeGen/PowerPC/ppc-rotate-clear.ll b/llvm/test/CodeGen/PowerPC/ppc-rotate-clear.ll
index f9d2c259a4c19..c88920b723796 100644
--- a/llvm/test/CodeGen/PowerPC/ppc-rotate-clear.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-rotate-clear.ll
@@ -11,11 +11,10 @@
define dso_local i64 @rotatemask32(i64 noundef %word) local_unnamed_addr #0 {
; AIX32-LABEL: rotatemask32:
; AIX32: # %bb.0: # %entry
-; AIX32-NEXT: cntlzw r5, r3
; AIX32-NEXT: cmplwi r3, 0
-; AIX32-NEXT: cntlzw r3, r4
-; AIX32-NEXT: addi r3, r3, 32
-; AIX32-NEXT: iseleq r3, r3, r5
+; AIX32-NEXT: cntlzw r5, r4
+; AIX32-NEXT: cntlzw r6, r3
+; AIX32-NEXT: iseleq r3, r5, r6
; AIX32-NEXT: rlwnm r4, r4, r3, 1, 31
; AIX32-NEXT: li r3, 0
; AIX32-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/rotl-2.ll b/llvm/test/CodeGen/PowerPC/rotl-2.ll
index 1ee30ac7ed491..f02630cbebd25 100644
--- a/llvm/test/CodeGen/PowerPC/rotl-2.ll
+++ b/llvm/test/CodeGen/PowerPC/rotl-2.ll
@@ -19,7 +19,7 @@ define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
; CHECK-LABEL: rotr32:
; CHECK: # %bb.0:
-; CHECK-NEXT: subfic 4, 4, 32
+; CHECK-NEXT: neg 4, 4
; CHECK-NEXT: rotlw 3, 3, 4
; CHECK-NEXT: blr
%shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
diff --git a/llvm/test/CodeGen/SystemZ/shift-04.ll b/llvm/test/CodeGen/SystemZ/shift-04.ll
index c91a7292604c8..fbc8bd2100d8e 100644
--- a/llvm/test/CodeGen/SystemZ/shift-04.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-04.ll
@@ -112,12 +112,10 @@ define i32 @f8(i32 %a, i32 %amt) {
ret i32 %or
}
-; Check the next value up, which without masking must use a separate
-; addition.
+; Check that a constant with zero demanded shift bits is eliminated.
define i32 @f9(i32 %a, i32 %amt) {
; CHECK-LABEL: f9:
; CHECK: # %bb.0:
-; CHECK-NEXT: afi %r3, 524288
; CHECK-NEXT: rll %r2, %r2, 0(%r3)
; CHECK-NEXT: br %r14
%add = add i32 %amt, 524288
@@ -147,7 +145,7 @@ define i32 @f10(i32 %a, i32 %amt) {
define i32 @f11(i32 %a, i32 %amt) {
; CHECK-LABEL: f11:
; CHECK: # %bb.0:
-; CHECK-NEXT: rll %r2, %r2, -524288(%r3)
+; CHECK-NEXT: rll %r2, %r2, 0(%r3)
; CHECK-NEXT: br %r14
%suba = sub i32 %amt, 524288
%subb = sub i32 32, %suba
diff --git a/llvm/test/CodeGen/SystemZ/shift-08.ll b/llvm/test/CodeGen/SystemZ/shift-08.ll
index c81097fd07e15..7b34203f1adef 100644
--- a/llvm/test/CodeGen/SystemZ/shift-08.ll
+++ b/llvm/test/CodeGen/SystemZ/shift-08.ll
@@ -113,12 +113,10 @@ define i64 @f8(i64 %a, i64 %amt) {
ret i64 %or
}
-; Check the next value up, which without masking must use a separate
-; addition.
+; Check that an out-of-range constant with zero low shift bits is eliminated.
define i64 @f9(i64 %a, i64 %amt) {
; CHECK-LABEL: f9:
; CHECK: # %bb.0:
-; CHECK-NEXT: afi %r3, 524288
; CHECK-NEXT: rllg %r2, %r2, 0(%r3)
; CHECK-NEXT: br %r14
%add = add i64 %amt, 524288
@@ -148,7 +146,7 @@ define i64 @f10(i64 %a, i64 %amt) {
define i64 @f11(i64 %a, i64 %amt) {
; CHECK-LABEL: f11:
; CHECK: # %bb.0:
-; CHECK-NEXT: rllg %r2, %r2, -524288(%r3)
+; CHECK-NEXT: rllg %r2, %r2, 0(%r3)
; CHECK-NEXT: br %r14
%suba = sub i64 %amt, 524288
%subb = sub i64 64, %suba
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