[llvm-branch-commits] [llvm] [RFC][AMDGPU] Remove DebugCounter-based WaitCnt debugging (PR #202937)
Pierre van Houtryve via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Jun 17 01:08:21 PDT 2026
https://github.com/Pierre-vh updated https://github.com/llvm/llvm-project/pull/202937
>From 15f1947e77469adaee29b491ac7aba71182f6dab Mon Sep 17 00:00:00 2001
From: pvanhout <pierre.vanhoutryve at amd.com>
Date: Wed, 10 Jun 2026 12:13:55 +0200
Subject: [PATCH] [RFC][AMDGPU] Remove DebugCounter-based WaitCnt debugging
It's 8 years old, only used by a handful of tests, and has not been updated
in a while except for maintenance as far as I can see.
I don't mind keeping it in if there are users of it, but right now it
looks like a dead feature. If we want some more elaborate waitcnt debugging,
we should have a modern, generic system that works on any waitcnt, not
something specific to 3 GFX9 counters.
---
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 51 +--------------------
llvm/test/CodeGen/AMDGPU/waitcnt-debug.mir | 44 ------------------
2 files changed, 1 insertion(+), 94 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/waitcnt-debug.mir
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 07214ac3a5b1e..632389b97fddd 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -40,7 +40,6 @@
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/IR/Dominators.h"
#include "llvm/InitializePasses.h"
-#include "llvm/Support/DebugCounter.h"
#include "llvm/TargetParser/AMDGPUTargetParser.h"
using namespace llvm;
@@ -50,13 +49,6 @@ using HWEvent = AMDGPU::HWEvent;
#define DEBUG_TYPE "si-insert-waitcnts"
-DEBUG_COUNTER(ForceExpCounter, DEBUG_TYPE "-forceexp",
- "Force emit s_waitcnt expcnt(0) instrs");
-DEBUG_COUNTER(ForceLgkmCounter, DEBUG_TYPE "-forcelgkm",
- "Force emit s_waitcnt lgkmcnt(0) instrs");
-DEBUG_COUNTER(ForceVMCounter, DEBUG_TYPE "-forcevm",
- "Force emit s_waitcnt vmcnt(0) instrs");
-
static cl::opt<bool>
ForceEmitZeroFlag("amdgpu-waitcnt-forcezero",
cl::desc("Force all waitcnt instrs to be emitted as "
@@ -421,11 +413,7 @@ class SIInsertWaitcnts {
AliasAnalysis *AA, MachineFunction &MF)
: MLI(MLI), PDT(PDT), AA(AA), MF(MF), ST(MF.getSubtarget<GCNSubtarget>()),
TII(*ST.getInstrInfo()), TRI(TII.getRegisterInfo()),
- MRI(MF.getRegInfo()) {
- (void)ForceExpCounter;
- (void)ForceLgkmCounter;
- (void)ForceVMCounter;
- }
+ MRI(MF.getRegInfo()) {}
const AMDGPU::HardwareLimits &getLimits() const { return Limits; }
@@ -438,42 +426,6 @@ class SIInsertWaitcnts {
bool mayStoreIncrementingDSCNT(const MachineInstr &MI) const;
bool run();
- void setForceEmitWaitcnt() {
-// For non-debug builds, ForceEmitWaitcnt has been initialized to false;
-// For debug builds, get the debug counter info and adjust if need be
-#ifndef NDEBUG
- if (DebugCounter::isCounterSet(ForceExpCounter) &&
- DebugCounter::shouldExecute(ForceExpCounter)) {
- ForceEmitWaitcnt[AMDGPU::EXP_CNT] = true;
- } else {
- ForceEmitWaitcnt[AMDGPU::EXP_CNT] = false;
- }
-
- if (DebugCounter::isCounterSet(ForceLgkmCounter) &&
- DebugCounter::shouldExecute(ForceLgkmCounter)) {
- ForceEmitWaitcnt[AMDGPU::DS_CNT] = true;
- ForceEmitWaitcnt[AMDGPU::KM_CNT] = true;
- } else {
- ForceEmitWaitcnt[AMDGPU::DS_CNT] = false;
- ForceEmitWaitcnt[AMDGPU::KM_CNT] = false;
- }
-
- if (DebugCounter::isCounterSet(ForceVMCounter) &&
- DebugCounter::shouldExecute(ForceVMCounter)) {
- ForceEmitWaitcnt[AMDGPU::LOAD_CNT] = true;
- ForceEmitWaitcnt[AMDGPU::SAMPLE_CNT] = true;
- ForceEmitWaitcnt[AMDGPU::BVH_CNT] = true;
- } else {
- ForceEmitWaitcnt[AMDGPU::LOAD_CNT] = false;
- ForceEmitWaitcnt[AMDGPU::SAMPLE_CNT] = false;
- ForceEmitWaitcnt[AMDGPU::BVH_CNT] = false;
- }
-
- ForceEmitWaitcnt[AMDGPU::VA_VDST] = false;
- ForceEmitWaitcnt[AMDGPU::VM_VSRC] = false;
-#endif // NDEBUG
- }
-
bool isAsync(const MachineInstr &MI) const {
if (!SIInstrInfo::isLDSDMA(MI))
return false;
@@ -2297,7 +2249,6 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(
MachineInstr &MI, WaitcntBrackets &ScoreBrackets,
MachineInstr *OldWaitcntInstr, PreheaderFlushFlags FlushFlags) {
LLVM_DEBUG(dbgs() << "\n*** GenerateWaitcntInstBefore: "; MI.print(dbgs()););
- setForceEmitWaitcnt();
assert(!isNonWaitcntMetaInst(MI));
diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-debug.mir b/llvm/test/CodeGen/AMDGPU/waitcnt-debug.mir
deleted file mode 100644
index 4bd8fde434621..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/waitcnt-debug.mir
+++ /dev/null
@@ -1,44 +0,0 @@
-# REQUIRES: asserts
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -debug-counter=si-insert-waitcnts-forcelgkm=0 -o - %s | FileCheck -check-prefixes=GCN,LGKM %s
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -debug-counter=si-insert-waitcnts-forceexp=0-1 -o - %s | FileCheck -check-prefixes=GCN,EXP %s
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -debug-counter=si-insert-waitcnts-forcevm=0-2 -o - %s | FileCheck -check-prefixes=GCN,VM %s
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -amdgpu-waitcnt-forcezero=1 -debug-counter=si-insert-waitcnts-forcevm=0-1 -o - %s | FileCheck -check-prefixes=GCN,ZERO %s
-
-# check that the waitcnt pass options that force insertion of waitcnt instructions are working as expected
-
-...
-# GCN-LABEL: name: waitcnt-debug
-# LGKM: S_WAITCNT .Lgkmcnt_0
-# LGKM-NEXT: S_NOP 0
-# LGKM-NEXT: S_NOP 0
-
-# EXP: S_WAITCNT .Expcnt_0
-# EXP-NEXT: S_NOP 0
-# EXP-NEXT: S_WAITCNT .Expcnt_0
-# EXP-NEXT: S_NOP 0
-
-# VM: S_WAITCNT .Vmcnt_0
-# VM-NEXT: S_NOP 0
-# VM-NEXT: S_WAITCNT .Vmcnt_0
-# VM-NEXT: S_NOP 0
-# VM-NEXT: S_WAITCNT .Vmcnt_0
-# VM-NEXT: S_NOP 0
-
-# ZERO: S_WAITCNT .Vmcnt_0_Expcnt_0_Lgkmcnt_0
-# ZERO-NEXT: S_NOP 0
-# ZERO-NEXT: S_WAITCNT .Vmcnt_0_Expcnt_0_Lgkmcnt_0
-# ZERO-NEXT: S_NOP 0
-# ZERO-NEXT: S_WAITCNT .Vmcnt_0_Expcnt_0_Lgkmcnt_0
-# ZERO-NEXT: S_NOP 0
-
-name: waitcnt-debug
-liveins:
-machineFunctionInfo:
- isEntryFunction: true
-body: |
- bb.0:
- S_NOP 0
- S_NOP 0
- S_NOP 0
- S_NOP 0
-...
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