[llvm-branch-commits] [llvm] [SelectionDAG] Keep split vector atomic store value in a vector register (PR #201566)

[Simon Pilgrim via llvm-branch-commits]

================
@@ -4742,16 +4742,47 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
 
 SDValue DAGTypeLegalizer::SplitVecOp_ATOMIC_STORE(AtomicSDNode *N) {
   SDLoc DL(N);
+  LLVMContext &Ctx = *DAG.getContext();
   SDValue StVal = N->getVal();
   EVT VT = StVal.getValueType();
+  EVT MemIntVT = EVT::getIntegerVT(Ctx, N->getMemoryVT().getSizeInBits());
+
+  // The store needs a single value spanning the full memory width. If the
+  // value can be held in a legal vector register, keep it there and extract
+  // the low integer element of the memory width. This lets the store be issued
+  // directly from a vector register (e.g. a single MOVQ/MOVD) instead of
+  // bitcasting the split vector straight to a scalar integer, which would
+  // reassemble the value element by element in GPRs.
+  //
+  // Reinterpret the value as a same-shaped integer vector first: an FP element
+  // type may not have a legal vector form (e.g. bfloat on SSE2) while the
+  // integer-of-element-size form does.
+  unsigned NumElts = VT.getVectorNumElements();
+  EVT IntEltVT = EVT::getIntegerVT(Ctx, VT.getScalarSizeInBits());
+  EVT IntVecVT = EVT::getVectorVT(Ctx, IntEltVT, NumElts);
----------------
RKSimon wrote:

```suggestion
  EVT IntVecVT = VT.changeVectorElementTypeToInteger();
  EVT IntEltVT = IntVecVT.getVectorElementType();
```

https://github.com/llvm/llvm-project/pull/201566