[llvm-branch-commits] [llvm] de1ff3e - [AMDGPU] Allow null operands in VImage tensor instructions (#200911)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Jun 5 09:27:17 PDT 2026
Author: Ryan Mitchell
Date: 2026-06-05T08:45:20-07:00
New Revision: de1ff3e2db8a207f366f33b8918079a5ed273d77
URL: https://github.com/llvm/llvm-project/commit/de1ff3e2db8a207f366f33b8918079a5ed273d77
DIFF: https://github.com/llvm/llvm-project/commit/de1ff3e2db8a207f366f33b8918079a5ed273d77.diff
LOG: [AMDGPU] Allow null operands in VImage tensor instructions (#200911)
NULL is equivalent to passing a block of SGPRs that are set to zero, and
is allowed for 3+ opnds.
Added:
Modified:
llvm/lib/Target/AMDGPU/MIMGInstructions.td
llvm/test/MC/AMDGPU/gfx1250_asm_vimage.s
llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s
llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vimage.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 0f31697f15688..90764c1a7850b 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -2183,8 +2183,8 @@ class VIMAGE_TENSOR_Pseudo<string opName, bit _UpTo2D = 0> :
bit UpTo2D = _UpTo2D;
let InOperandList = !if(UpTo2D, (ins SReg_128_XNULL:$vaddr0, SReg_256_XNULL:$vaddr1, R128A16:$r128, CPol:$cpol),
- (ins SReg_128_XNULL:$vaddr0, SReg_256_XNULL:$vaddr1, SReg_128_XNULL:$vaddr2,
- SReg_128_XNULL:$vaddr3, R128A16:$r128, CPol:$cpol));
+ (ins SReg_128_XNULL:$vaddr0, SReg_256_XNULL:$vaddr1, SReg_128:$vaddr2,
+ SReg_128:$vaddr3, R128A16:$r128, CPol:$cpol));
string AsmOperands = " $vaddr0, $vaddr1"#!if(UpTo2D, "", ", $vaddr2, $vaddr3")#"$r128$cpol";
}
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vimage.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vimage.s
index f799a54fdc775..48e61e4f6303e 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vimage.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vimage.s
@@ -26,6 +26,18 @@ tensor_store_from_lds s[0:3], s[4:11] th:TH_STORE_BYPASS scope:SCOPE_SYS
// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU (gfx1200): tensor_store_from_lds
// GFX1250: tensor_store_from_lds s[0:3], s[4:11] th:TH_STORE_BYPASS scope:SCOPE_SYS ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x3c,0x7c,0x00,0x04,0x7c,0x7c]
+tensor_store_from_lds s[0:3], s[4:11], null, null th:TH_STORE_NT_HT scope:SCOPE_DEV
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU (gfx1200): tensor_store_from_lds
+// GFX1250: tensor_store_from_lds s[0:3], s[4:11], null, null th:TH_STORE_NT_HT scope:SCOPE_DEV ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x7c,0x7c]
+
+tensor_store_from_lds s[0:3], s[4:11], null, s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU (gfx1200): tensor_store_from_lds
+// GFX1250: tensor_store_from_lds s[0:3], s[4:11], null, s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x7c,0x10]
+
+tensor_store_from_lds s[0:3], s[4:11], s[12:15], null th:TH_STORE_NT_HT scope:SCOPE_DEV
+// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU (gfx1200): tensor_store_from_lds
+// GFX1250: tensor_store_from_lds s[0:3], s[4:11], s[12:15], null th:TH_STORE_NT_HT scope:SCOPE_DEV ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x0c,0x7c]
+
tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19]
// GFX12-ERR: :[[@LINE-1]]:1: error: instruction not supported on this GPU (gfx1200): tensor_store_from_lds
// GFX1250: tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x00,0x7c,0x00,0x04,0x0c,0x10]
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s b/llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s
index 2f911ae79c00f..d9f5b8047e701 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_vimage_err.s
@@ -37,12 +37,6 @@ tensor_load_to_lds null, s[4:11], s[12:15], s[16:19]
tensor_load_to_lds s[0:3], null, s[12:15], s[16:19]
// GFX1250-ERR: :[[@LINE-1]]:28: error: invalid operand for instruction
-tensor_load_to_lds s[0:3], s[4:11], null, s[16:19]
-// GFX1250-ERR: :[[@LINE-1]]:37: error: invalid operand for instruction
-
-tensor_load_to_lds s[0:3], s[4:11], s[12:15], null
-// GFX1250-ERR: :[[@LINE-1]]:47: error: invalid operand for instruction
-
tensor_store_from_lds null, s[4:11]
// GFX1250-ERR: :[[@LINE-1]]:23: error: invalid operand for instruction
@@ -55,12 +49,6 @@ tensor_store_from_lds null, s[4:11], s[12:15], s[16:19]
tensor_store_from_lds s[0:3], null, s[12:15], s[16:19]
// GFX1250-ERR: :[[@LINE-1]]:31: error: invalid operand for instruction
-tensor_store_from_lds s[0:3], s[4:11], null, s[16:19]
-// GFX1250-ERR: :[[@LINE-1]]:40: error: invalid operand for instruction
-
-tensor_store_from_lds s[0:3], s[4:11], s[12:15], null
-// GFX1250-ERR: :[[@LINE-1]]:50: error: invalid operand for instruction
-
tensor_load_to_lds s[14:17], s[4:11]
// GFX1250-ERR: :[[@LINE-1]]:20: error: invalid register alignment
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vimage.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vimage.txt
index a2132f1138969..0bc505e848741 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vimage.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vimage.txt
@@ -19,6 +19,15 @@
0x01,0x40,0x71,0xd0,0x00,0x00,0x3c,0x7c,0x00,0x04,0x7c,0x7c
# GFX1250: tensor_store_from_lds s[0:3], s[4:11] th:TH_STORE_BYPASS scope:SCOPE_SYS ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x3c,0x7c,0x00,0x04,0x7c,0x7c]
+0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x7c,0x7c
+# GFX1250: tensor_store_from_lds s[0:3], s[4:11] th:TH_STORE_NT_HT scope:SCOPE_DEV ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x7c,0x7c]
+
+0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x7c,0x10
+# GFX1250: tensor_store_from_lds s[0:3], s[4:11], null, s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x7c,0x10]
+
+0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x0c,0x7c
+# GFX1250: tensor_store_from_lds s[0:3], s[4:11], s[12:15], null th:TH_STORE_NT_HT scope:SCOPE_DEV ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x68,0x7c,0x00,0x04,0x0c,0x7c]
+
0x01,0x40,0x71,0xd0,0x00,0x00,0x00,0x7c,0x00,0x04,0x0c,0x10
# GFX1250: tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] ; encoding: [0x01,0x40,0x71,0xd0,0x00,0x00,0x00,0x7c,0x00,0x04,0x0c,0x10]
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