[llvm-branch-commits] [llvm] [SelectionDAG] isGuaranteedNotToBeUndefOrPoison - add ISD::SELECT handling (PR #200934)
Krzysztof Drewniak via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Jun 4 12:54:32 PDT 2026
https://github.com/krzysz00 updated https://github.com/llvm/llvm-project/pull/200934
>From c2fbbaf6873399da472c44e2958ee94ba9cdcae3 Mon Sep 17 00:00:00 2001
From: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: Fri, 29 May 2026 22:35:59 +0000
Subject: [PATCH 1/3] [SelectionDAG] Track demanded select elements in noundef
checks
Propagate demanded elements through to the two arms of a select, and
check the condition with or without demanded elements depending on if
it's a vector or not.
AI note: an LLM generated the code and the test, I've read them
Co-Authored-By: OpenAI Codex <codex at openai.com>
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 19 +++++++++++++++++--
llvm/test/CodeGen/X86/freeze-vector.ll | 11 -----------
2 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 5d0ada4a1790a..6e997a43eec0c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5804,6 +5804,22 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op,
case ISD::SPLAT_VECTOR:
return isGuaranteedNotToBeUndefOrPoison(Op.getOperand(0), Kind, Depth + 1);
+ case ISD::SELECT:
+ case ISD::VSELECT: {
+ SDValue Cond = Op.getOperand(0);
+ bool CondIsVector = Cond.getValueType().isVector();
+ return !canCreateUndefOrPoison(Op, DemandedElts, Kind,
+ /*ConsiderFlags*/ true, Depth) &&
+ (CondIsVector
+ ? isGuaranteedNotToBeUndefOrPoison(Cond, DemandedElts, Kind,
+ Depth + 1)
+ : isGuaranteedNotToBeUndefOrPoison(Cond, Kind, Depth + 1)) &&
+ isGuaranteedNotToBeUndefOrPoison(Op.getOperand(1), DemandedElts,
+ Kind, Depth + 1) &&
+ isGuaranteedNotToBeUndefOrPoison(Op.getOperand(2), DemandedElts,
+ Kind, Depth + 1);
+ }
+
case ISD::VECTOR_SHUFFLE: {
APInt DemandedLHS, DemandedRHS;
auto *SVN = cast<ShuffleVectorSDNode>(Op);
@@ -5854,8 +5870,7 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op,
case ISD::ZERO_EXTEND:
case ISD::SIGN_EXTEND:
case ISD::ANY_EXTEND:
- case ISD::TRUNCATE:
- case ISD::VSELECT: {
+ case ISD::TRUNCATE: {
// If Op can't create undef/poison and none of its operands are undef/poison
// then Op is never undef/poison. A difference from the more common check
// below, outside the switch, is that we handle elementwise operations for
diff --git a/llvm/test/CodeGen/X86/freeze-vector.ll b/llvm/test/CodeGen/X86/freeze-vector.ll
index 5f19a3d295bcc..5acfa98d0551e 100644
--- a/llvm/test/CodeGen/X86/freeze-vector.ll
+++ b/llvm/test/CodeGen/X86/freeze-vector.ll
@@ -772,17 +772,6 @@ define i32 @freeze_select_scalar_demanded(i1 %c, <2 x i32> %a, <2 x i32> %b, <2
;
; X64-LABEL: freeze_select_scalar_demanded:
; X64: # %bb.0:
-; X64-NEXT: testb $1, %dil
-; X64-NEXT: jne .LBB27_1
-; X64-NEXT: # %bb.2:
-; X64-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
-; X64-NEXT: vpsubd %xmm1, %xmm2, %xmm1
-; X64-NEXT: jmp .LBB27_3
-; X64-NEXT: .LBB27_1:
-; X64-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483647,2147483647,2147483647,2147483647]
-; X64-NEXT: vpaddd %xmm2, %xmm1, %xmm1
-; X64-NEXT: .LBB27_3:
-; X64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X64-NEXT: vmovd %xmm0, %eax
; X64-NEXT: retq
%poisonable.b = add nsw <2 x i32> %b, <i32 2147483647, i32 2147483647>
>From bcd2e2eaf285fafbca082f8e504aa6c5c8acd9d1 Mon Sep 17 00:00:00 2001
From: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: Wed, 3 Jun 2026 18:35:23 +0000
Subject: [PATCH 2/3] Review feedback
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 6e997a43eec0c..4c0a8007e3fbd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5804,16 +5804,11 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op,
case ISD::SPLAT_VECTOR:
return isGuaranteedNotToBeUndefOrPoison(Op.getOperand(0), Kind, Depth + 1);
- case ISD::SELECT:
- case ISD::VSELECT: {
+ case ISD::SELECT: {
SDValue Cond = Op.getOperand(0);
- bool CondIsVector = Cond.getValueType().isVector();
return !canCreateUndefOrPoison(Op, DemandedElts, Kind,
/*ConsiderFlags*/ true, Depth) &&
- (CondIsVector
- ? isGuaranteedNotToBeUndefOrPoison(Cond, DemandedElts, Kind,
- Depth + 1)
- : isGuaranteedNotToBeUndefOrPoison(Cond, Kind, Depth + 1)) &&
+ isGuaranteedNotToBeUndefOrPoison(Cond, Kind, Depth + 1) &&
isGuaranteedNotToBeUndefOrPoison(Op.getOperand(1), DemandedElts,
Kind, Depth + 1) &&
isGuaranteedNotToBeUndefOrPoison(Op.getOperand(2), DemandedElts,
@@ -5870,7 +5865,8 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op,
case ISD::ZERO_EXTEND:
case ISD::SIGN_EXTEND:
case ISD::ANY_EXTEND:
- case ISD::TRUNCATE: {
+ case ISD::TRUNCATE:
+ case ISD::VSELECT: {
// If Op can't create undef/poison and none of its operands are undef/poison
// then Op is never undef/poison. A difference from the more common check
// below, outside the switch, is that we handle elementwise operations for
>From 89054bf87b0f62001f7de7709de9127a0db8803d Mon Sep 17 00:00:00 2001
From: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: Thu, 4 Jun 2026 18:52:17 +0000
Subject: [PATCH 3/3] Review feedback I forgot to push lol
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 4c0a8007e3fbd..e752d00117b2d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5805,10 +5805,10 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op,
return isGuaranteedNotToBeUndefOrPoison(Op.getOperand(0), Kind, Depth + 1);
case ISD::SELECT: {
- SDValue Cond = Op.getOperand(0);
return !canCreateUndefOrPoison(Op, DemandedElts, Kind,
/*ConsiderFlags*/ true, Depth) &&
- isGuaranteedNotToBeUndefOrPoison(Cond, Kind, Depth + 1) &&
+ isGuaranteedNotToBeUndefOrPoison(Op.getOperand(0), Kind,
+ Depth + 1) &&
isGuaranteedNotToBeUndefOrPoison(Op.getOperand(1), DemandedElts,
Kind, Depth + 1) &&
isGuaranteedNotToBeUndefOrPoison(Op.getOperand(2), DemandedElts,
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