[llvm-branch-commits] [llvm] [LoopInterchange] Prevent to interchange when memory-related calls exist (PR #200828)

[Ryotaro Kasuga via llvm-branch-commits]

https://github.com/kasuga-fj created https://github.com/llvm/llvm-project/pull/200828

None

>From c0f8fa3543acae89efaafdae811e3fc2186e3bba Mon Sep 17 00:00:00 2001
From: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: Mon, 1 Jun 2026 14:03:06 +0000
Subject: [PATCH] [LoopInterchange] Prevent to interchange when memory-related
 calls exist

---
 .../lib/Transforms/Scalar/LoopInterchange.cpp |  6 +++--
 .../Transforms/LoopInterchange/memory-attr.ll | 26 +++++--------------
 2 files changed, 11 insertions(+), 21 deletions(-)

diff --git a/llvm/lib/Transforms/Scalar/LoopInterchange.cpp b/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
index 9d424ae13e28a..1af873cb6ecfe 100644
--- a/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
@@ -1474,8 +1474,10 @@ bool LoopInterchangeLegality::canInterchangeLoops(unsigned InnerLoopId,
   for (auto *BB : OuterLoop->blocks())
     for (Instruction &I : *BB)
       if (CallInst *CI = dyn_cast<CallInst>(&I)) {
-        // readnone functions do not prevent interchanging.
-        if (CI->onlyWritesMemory() || isa<PseudoProbeInst>(CI))
+        if (isa<PseudoProbeInst>(CI))
+          continue;
+        // Functions which don't access memories do not prevent interchanging.
+        if (CI->doesNotAccessMemory())
           continue;
         LLVM_DEBUG(
             dbgs() << "Loops with call instructions cannot be interchanged "
diff --git a/llvm/test/Transforms/LoopInterchange/memory-attr.ll b/llvm/test/Transforms/LoopInterchange/memory-attr.ll
index c32f48ef63694..c2f0c74167b5e 100644
--- a/llvm/test/Transforms/LoopInterchange/memory-attr.ll
+++ b/llvm/test/Transforms/LoopInterchange/memory-attr.ll
@@ -8,36 +8,24 @@
 ; The writeonly call may write to `%A` at some unknown index, so we cannot
 ; interchange the loops.
 ;
-; FIXME: These loops are now interchanged.
-;
 define void @call_writeonly(ptr %A) {
 ; CHECK-LABEL: define void @call_writeonly(
 ; CHECK-SAME: ptr [[A:%.*]]) {
-; CHECK-NEXT:  [[INNER_PREHEADER:.*:]]
-; CHECK-NEXT:    br label %[[INNER:.*]]
-; CHECK:       [[OUTER_HEADER_PREHEADER1:.*]]:
-; CHECK-NEXT:    br label %[[OUTER_HEADER_PREHEADER:.*]]
-; CHECK:       [[OUTER_HEADER_PREHEADER]]:
-; CHECK-NEXT:    [[I:%.*]] = phi i64 [ [[I_NEXT:%.*]], %[[OUTER_LATCH:.*]] ], [ 0, %[[OUTER_HEADER_PREHEADER1]] ]
-; CHECK-NEXT:    br label %[[INNER_SPLIT1:.*]]
-; CHECK:       [[INNER]]:
+; CHECK-NEXT:  [[INNER:.*]]:
 ; CHECK-NEXT:    br label %[[INNER1:.*]]
 ; CHECK:       [[INNER1]]:
-; CHECK-NEXT:    [[J:%.*]] = phi i64 [ [[TMP2:%.*]], %[[INNER_SPLIT:.*]] ], [ 0, %[[INNER]] ]
-; CHECK-NEXT:    br label %[[OUTER_HEADER_PREHEADER1]]
-; CHECK:       [[INNER_SPLIT1]]:
+; CHECK-NEXT:    [[I:%.*]] = phi i64 [ 0, %[[INNER]] ], [ [[I_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
+; CHECK-NEXT:    br label %[[OUTER_HEADER_PREHEADER1:.*]]
+; CHECK:       [[OUTER_HEADER_PREHEADER1]]:
+; CHECK-NEXT:    [[J:%.*]] = phi i64 [ 0, %[[INNER1]] ], [ [[TMP2:%.*]], %[[OUTER_HEADER_PREHEADER1]] ]
 ; CHECK-NEXT:    call void @writeonly(ptr [[A]])
-; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[J]], 1
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i64 [[TMP0]], 100
-; CHECK-NEXT:    br label %[[OUTER_LATCH]]
-; CHECK:       [[INNER_SPLIT]]:
 ; CHECK-NEXT:    [[TMP2]] = add i64 [[J]], 1
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[TMP2]], 100
-; CHECK-NEXT:    br i1 [[TMP3]], label %[[EXIT:.*]], label %[[INNER1]]
+; CHECK-NEXT:    br i1 [[TMP3]], label %[[OUTER_LATCH]], label %[[OUTER_HEADER_PREHEADER1]]
 ; CHECK:       [[OUTER_LATCH]]:
 ; CHECK-NEXT:    [[I_NEXT]] = add i64 [[I]], 1
 ; CHECK-NEXT:    [[EC_OUTER:%.*]] = icmp eq i64 [[I_NEXT]], 100
-; CHECK-NEXT:    br i1 [[EC_OUTER]], label %[[INNER_SPLIT]], label %[[OUTER_HEADER_PREHEADER]]
+; CHECK-NEXT:    br i1 [[EC_OUTER]], label %[[EXIT:.*]], label %[[INNER1]]
 ; CHECK:       [[EXIT]]:
 ; CHECK-NEXT:    ret void
 ;