[llvm-branch-commits] [llvm] [InlineSpiller][AMDGPU] Implement subreg reload during RA spill (PR #175002)

[Quentin Colombet via llvm-branch-commits]

================
@@ -1248,18 +1249,62 @@ void InlineSpiller::spillAroundUses(Register Reg) {
 
     // Create a new virtual register for spill/fill.
     // FIXME: Infer regclass from instruction alone.
-    Register NewVReg = Edit->createFrom(Reg);
+
+    unsigned SubReg = 0;
+    LaneBitmask CoveringLanes = LaneBitmask::getNone();
----------------
qcolombet wrote:

I could be missing something but I would expect the code to only need to query the LiveInterval.

Like:
```
AliveLanes = None;
for (subrange : LI) {
  if (subrange.liveAt(SlotIndexOfMI)) // <-- read or write depending on reload or spill
    AliveLanes |= subrange.LaneMask;
}
```

https://github.com/llvm/llvm-project/pull/175002