[llvm-branch-commits] [llvm] [InlineSpiller][AMDGPU] Implement subreg reload during RA spill (PR #175002)

[Christudasan Devadasan via llvm-branch-commits]

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@@ -1248,18 +1249,62 @@ void InlineSpiller::spillAroundUses(Register Reg) {
 
     // Create a new virtual register for spill/fill.
     // FIXME: Infer regclass from instruction alone.
-    Register NewVReg = Edit->createFrom(Reg);
+
+    unsigned SubReg = 0;
+    LaneBitmask CoveringLanes = LaneBitmask::getNone();
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cdevadas wrote:

This code is inside the loop that processes each MI that refers the virtual register (Reg). As you know, a reload is inserted for each use. The Ops being used here is pre-extracted data that contains the MI and the OpIdx of the current use. Ops mostly has a single entry, but it can contain multiple entries for copy bundles. What you mentioned with LI would be helpful for capturing the entire set of alive lanes of the virtual register. However, in this context, I’m specifically capturing the subRegMask, particularly important for copy bundles that may span multiple disjoint sub-registers of the tuple. I’ve mentioned that in the comment as well.

https://github.com/llvm/llvm-project/pull/175002