[llvm-branch-commits] [llvm] [AArch64][llvm] Gate some `tlbip` insns with either +tlbid or +d128 (PR #178913)

[via llvm-branch-commits]

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@@ -4267,20 +4267,22 @@ bool AArch64AsmParser::parseSyspAlias(StringRef Name, SMLoc NameLoc,
     const AArch64TLBIP::TLBIP *TLBIPorig = AArch64TLBIP::lookupTLBIPByName(Op);
     if (!TLBIPorig)
       return TokError("invalid operand for TLBIP instruction");
-    if (!getSTI().hasFeature(AArch64::FeatureD128) &&
-        !getSTI().hasFeature(AArch64::FeatureAll))
-      return TokError("instruction requires: d128");
     const AArch64TLBIP::TLBIP TLBIP(
         TLBIPorig->Name, TLBIPorig->Encoding | (HasnXSQualifier ? (1 << 7) : 0),
-        TLBIPorig->NeedsReg, TLBIPorig->OptionalReg,
+        TLBIPorig->NeedsReg, TLBIPorig->OptionalReg, TLBIPorig->AllowTLBID,
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Lukacma wrote:

Okay I don't think TLBIP variable is necessary here at all. you can just use TLBIPOrig.

https://github.com/llvm/llvm-project/pull/178913