[llvm-branch-commits] [llvm] [AArch64][llvm] Gate some `tlbip` insns with either +tlbid or +d128 (PR #178913)

[via llvm-branch-commits]

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@@ -897,18 +897,27 @@ defm TLBIP : TLBITableBase;
 
 multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm,
              bits<3> op2, bit needsreg = 1, bit optionalreg = 0> {
+  defvar HasE1IS = !ne(!find(name, "E1IS"), -1);
+  defvar HasE1OS = !ne(!find(name, "E1OS"), -1);
+  defvar HasE2IS = !ne(!find(name, "E2IS"), -1);
+  defvar HasE2OS = !ne(!find(name, "E2OS"), -1);
+  defvar allowTLBID = !or(!or(HasE1IS, HasE1OS), !or(HasE2IS, HasE2OS));
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Lukacma wrote:

Adding the check to C++ would probably be the cleanest solution, but then we would split definition of the instruction into 2 files, which I think would confuse people. So I think its best to specify the instruction completely in tablegen if we can. I see your point about increasing the table size now, but I think we can just use !match if you need to use regexes. Or did that not work for you?

https://github.com/llvm/llvm-project/pull/178913