[llvm-branch-commits] [llvm] [AArch64][llvm] Gate some `tlbip` insns with either +tlbid or +d128 (PR #178913)

[via llvm-branch-commits]

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@@ -877,13 +877,19 @@ class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
 
 class TLBIPEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
                  bits<3> op2, bit needsreg, bit optionalreg>
-  : TLBICommon<name, op1, crn, crm, op2, needsreg, optionalreg>;
+  : TLBICommon<name, op1, crn, crm, op2, needsreg, optionalreg> {
+  bit AllowTLBID = 0;
+}
 
-multiclass TLBITableBase {
+multiclass TLBITableBase<bit WithAllowTLBID> {
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Lukacma wrote:

I think this whole thing could be simplified if you past a list of extra fields to add to the table here. Then you just need to concat Fields and extra fields and you have your table

https://github.com/llvm/llvm-project/pull/178913