[llvm-branch-commits] [llvm] a112946 - fix bug in performANDORCSELCombine
Karl Meakin via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Sep 23 19:37:09 PDT 2022
Author: Karl Meakin
Date: 2022-09-24T02:13:29+01:00
New Revision: a11294617361e29de69dd52a0c07bae0cc6b998c
URL: https://github.com/llvm/llvm-project/commit/a11294617361e29de69dd52a0c07bae0cc6b998c
DIFF: https://github.com/llvm/llvm-project/commit/a11294617361e29de69dd52a0c07bae0cc6b998c.diff
LOG: fix bug in performANDORCSELCombine
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/ccmn.ll
llvm/test/CodeGen/AArch64/fccmp.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index cec26c133e7d..4ab171841abd 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -15034,29 +15034,27 @@ static SDValue performANDORCSELCombine(SDNode *N, SelectionDAG &DAG) {
if (!Cmp0->hasOneUse() || !Cmp1->hasOneUse())
return SDValue();
- unsigned Opcode = 0;
+ unsigned Opcode;
bool Swap = false;
- if (Cmp0.getOpcode() != AArch64ISD::SUBS &&
- Cmp1.getOpcode() == AArch64ISD::SUBS) {
+ if (Cmp1.getOpcode() == AArch64ISD::SUBS) {
Opcode = AArch64ISD::CCMP;
} else if (Cmp0.getOpcode() == AArch64ISD::SUBS) {
Opcode = AArch64ISD::CCMP;
Swap = true;
- } else if (Cmp0.getOpcode() == AArch64ISD::ADDS) {
- Opcode = AArch64ISD::CCMN;
} else if (Cmp1.getOpcode() == AArch64ISD::ADDS) {
Opcode = AArch64ISD::CCMN;
+ } else if (Cmp0.getOpcode() == AArch64ISD::ADDS) {
+ Opcode = AArch64ISD::CCMN;
Swap = true;
- } else if (Cmp0.getOpcode() == AArch64ISD::FCMP) {
- Opcode = AArch64ISD::FCCMP;
} else if (Cmp1.getOpcode() == AArch64ISD::FCMP) {
Opcode = AArch64ISD::FCCMP;
+ } else if (Cmp0.getOpcode() == AArch64ISD::FCMP) {
+ Opcode = AArch64ISD::FCCMP;
Swap = true;
- }
-
- if (Opcode == 0)
+ } else {
return SDValue();
+ }
if (Swap) {
std::swap(Cmp0, Cmp1);
diff --git a/llvm/test/CodeGen/AArch64/ccmn.ll b/llvm/test/CodeGen/AArch64/ccmn.ll
index 7532acac6bf3..7996062108af 100644
--- a/llvm/test/CodeGen/AArch64/ccmn.ll
+++ b/llvm/test/CodeGen/AArch64/ccmn.ll
@@ -5,8 +5,8 @@
define i1 @w0_eq_minus_1_and_w1_eq_minus_2(i32 %0, i32 %1) {
; CHECK-LABEL: w0_eq_minus_1_and_w1_eq_minus_2:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmn w1, #2
-; CHECK-NEXT: ccmn w0, #1, #0, eq
+; CHECK-NEXT: cmn w0, #1
+; CHECK-NEXT: ccmn w1, #2, #0, eq
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%3 = icmp eq i32 %0, -1
@@ -19,8 +19,8 @@ define i1 @w0_eq_minus_1_and_w1_eq_minus_2(i32 %0, i32 %1) {
define i1 @w0_eq_minus_30_and_w1_eq_minus_31(i32 %0, i32 %1) {
; CHECK-LABEL: w0_eq_minus_30_and_w1_eq_minus_31:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmn w1, #31
-; CHECK-NEXT: ccmn w0, #30, #0, eq
+; CHECK-NEXT: cmn w0, #30
+; CHECK-NEXT: ccmn w1, #31, #0, eq
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%3 = icmp eq i32 %0, -30
@@ -33,8 +33,8 @@ define i1 @w0_eq_minus_30_and_w1_eq_minus_31(i32 %0, i32 %1) {
define i1 @x0_eq_minus_1_and_x1_eq_minus_2(i64 %0, i64 %1) {
; CHECK-LABEL: x0_eq_minus_1_and_x1_eq_minus_2:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmn x1, #2
-; CHECK-NEXT: ccmn x0, #1, #0, eq
+; CHECK-NEXT: cmn x0, #1
+; CHECK-NEXT: ccmn x1, #2, #0, eq
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%3 = icmp eq i64 %0, -1
@@ -47,8 +47,8 @@ define i1 @x0_eq_minus_1_and_x1_eq_minus_2(i64 %0, i64 %1) {
define i1 @x0_eq_minus_30_and_x1_eq_minus_31(i64 %0, i64 %1) {
; CHECK-LABEL: x0_eq_minus_30_and_x1_eq_minus_31:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmn x1, #31
-; CHECK-NEXT: ccmn x0, #30, #0, eq
+; CHECK-NEXT: cmn x0, #30
+; CHECK-NEXT: ccmn x1, #31, #0, eq
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%3 = icmp eq i64 %0, -30
diff --git a/llvm/test/CodeGen/AArch64/fccmp.ll b/llvm/test/CodeGen/AArch64/fccmp.ll
index 6d0f11918f40..4e74b785cad2 100644
--- a/llvm/test/CodeGen/AArch64/fccmp.ll
+++ b/llvm/test/CodeGen/AArch64/fccmp.ll
@@ -31,9 +31,10 @@ define i1 @fcmp_and2(float %0, float %1, float %2, float %3) {
define i1 @fcmp_and3(float %0, float %1, float %2, float %3, float %4, float %5) {
; SDISEL-LABEL: fcmp_and3:
; SDISEL: // %bb.0:
-; SDISEL-NEXT: fcmp s4, s5
-; SDISEL-NEXT: fccmp s2, s3, #4, ne
-; SDISEL-NEXT: cset w0, gt
+; SDISEL-NEXT: fcmp s0, s1
+; SDISEL-NEXT: fccmp s2, s3, #4, mi
+; SDISEL-NEXT: fccmp s4, s5, #4, gt
+; SDISEL-NEXT: cset w0, ne
; SDISEL-NEXT: ret
;
; GISEL-LABEL: fcmp_and3:
@@ -59,9 +60,11 @@ define i1 @fcmp_and3(float %0, float %1, float %2, float %3, float %4, float %5)
define i1 @cmp_and4(float %0, float %1, float %2, float %3, float %4, float %5, float %6, float %7) {
; SDISEL-LABEL: cmp_and4:
; SDISEL: // %bb.0:
-; SDISEL-NEXT: fcmp s6, s7
-; SDISEL-NEXT: fccmp s2, s3, #4, eq
-; SDISEL-NEXT: cset w0, gt
+; SDISEL-NEXT: fcmp s0, s1
+; SDISEL-NEXT: fccmp s2, s3, #4, mi
+; SDISEL-NEXT: fccmp s4, s5, #4, gt
+; SDISEL-NEXT: fccmp s6, s7, #0, ne
+; SDISEL-NEXT: cset w0, eq
; SDISEL-NEXT: ret
;
; GISEL-LABEL: cmp_and4:
@@ -115,9 +118,10 @@ define i1 @cmp_or2(float %0, float %1, float %2, float %3) {
define i1 @cmp_or3(float %0, float %1, float %2, float %3, float %4, float %5) {
; SDISEL-LABEL: cmp_or3:
; SDISEL: // %bb.0:
-; SDISEL-NEXT: fcmp s4, s5
-; SDISEL-NEXT: fccmp s2, s3, #0, eq
-; SDISEL-NEXT: cset w0, gt
+; SDISEL-NEXT: fcmp s0, s1
+; SDISEL-NEXT: fccmp s2, s3, #0, pl
+; SDISEL-NEXT: fccmp s4, s5, #0, le
+; SDISEL-NEXT: cset w0, ne
; SDISEL-NEXT: ret
;
; GISEL-LABEL: cmp_or3:
@@ -143,9 +147,11 @@ define i1 @cmp_or3(float %0, float %1, float %2, float %3, float %4, float %5) {
define i1 @cmp_or4(float %0, float %1, float %2, float %3, float %4, float %5, float %6, float %7) {
; SDISEL-LABEL: cmp_or4:
; SDISEL: // %bb.0:
-; SDISEL-NEXT: fcmp s6, s7
-; SDISEL-NEXT: fccmp s2, s3, #0, ne
-; SDISEL-NEXT: cset w0, gt
+; SDISEL-NEXT: fcmp s0, s1
+; SDISEL-NEXT: fccmp s2, s3, #0, pl
+; SDISEL-NEXT: fccmp s4, s5, #0, le
+; SDISEL-NEXT: fccmp s6, s7, #4, eq
+; SDISEL-NEXT: cset w0, eq
; SDISEL-NEXT: ret
;
; GISEL-LABEL: cmp_or4:
@@ -200,9 +206,10 @@ define i1 @true_or2(float %0, float %1) {
define i1 @true_or3(float %0, float %1, float %2) {
; SDISEL-LABEL: true_or3:
; SDISEL: // %bb.0:
-; SDISEL-NEXT: movi d0, #0000000000000000
-; SDISEL-NEXT: fcmp s2, #0.0
-; SDISEL-NEXT: fccmp s1, s0, #0, eq
+; SDISEL-NEXT: movi d3, #0000000000000000
+; SDISEL-NEXT: fcmp s0, #0.0
+; SDISEL-NEXT: fccmp s1, s3, #0, eq
+; SDISEL-NEXT: fccmp s2, s3, #0, eq
; SDISEL-NEXT: cset w0, ne
; SDISEL-NEXT: ret
;
@@ -253,9 +260,10 @@ define i1 @true_and2(float %0, float %1) {
define i1 @true_and3(float %0, float %1, float %2) {
; SDISEL-LABEL: true_and3:
; SDISEL: // %bb.0:
-; SDISEL-NEXT: movi d0, #0000000000000000
-; SDISEL-NEXT: fcmp s2, #0.0
-; SDISEL-NEXT: fccmp s1, s0, #4, ne
+; SDISEL-NEXT: movi d3, #0000000000000000
+; SDISEL-NEXT: fcmp s0, #0.0
+; SDISEL-NEXT: fccmp s1, s3, #4, ne
+; SDISEL-NEXT: fccmp s2, s3, #4, ne
; SDISEL-NEXT: cset w0, ne
; SDISEL-NEXT: ret
;
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