[llvm-branch-commits] [llvm] e19be41 - [RISCV] Add another test showing incorrect BUILD_VECTOR lowering

[Tom Stellard via llvm-branch-commits]

Author: Fraser Cormack
Date: 2022-04-25T20:27:35-07:00
New Revision: e19be4195b8700ee48a84a50e65b1d4612b22cca

URL: https://github.com/llvm/llvm-project/commit/e19be4195b8700ee48a84a50e65b1d4612b22cca
DIFF: https://github.com/llvm/llvm-project/commit/e19be4195b8700ee48a84a50e65b1d4612b22cca.diff

LOG: [RISCV] Add another test showing incorrect BUILD_VECTOR lowering

This test shows a (contrived) BUILD_VECTOR which is correctly identified
as a sequence of ((vid * -3) / 8) + 5. However, the issue is that using
shift-right for the divide is invalid as the step values are negative.

This patch just adds the test: the fix is added in D123796.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D123989

(cherry picked from commit 627e21048a2c040d3e353cc4f0eb8f207b6ea61c)

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
index 085f5bc1d8493..3e10b0f3a49c5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -726,3 +726,18 @@ define <4 x i8> @buildvec_not_vid_v4i8_2() {
 ; CHECK-NEXT:    ret
   ret <4 x i8> <i8 3, i8 3, i8 1, i8 0>
 }
+
+; FIXME: This is not a valid way to emit this vid sequence: shift-right for
+; division only works for non-negative numbers!
+define <16 x i8> @buildvec_not_vid_v16i8() {
+; CHECK-LABEL: buildvec_not_vid_v16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    li a0, -3
+; CHECK-NEXT:    vmul.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 3
+; CHECK-NEXT:    vadd.vi v8, v8, 5
+; CHECK-NEXT:    ret
+  ret <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 3, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0>
+}