[llvm-branch-commits] [compiler-rt] 09fba23 - [compiler-rt] Implement __clear_cache on FreeBSD/powerpc

[Tom Stellard via llvm-branch-commits]

Author: Carlo Marcelo Arenas Belón
Date: 2022-04-18T17:03:57-07:00
New Revision: 09fba23d41f775e1cee48f56061710d5861c48d2

URL: https://github.com/llvm/llvm-project/commit/09fba23d41f775e1cee48f56061710d5861c48d2
DIFF: https://github.com/llvm/llvm-project/commit/09fba23d41f775e1cee48f56061710d5861c48d2.diff

LOG: [compiler-rt] Implement __clear_cache on FreeBSD/powerpc

dd9173420f06 (Add clear_cache implementation for ppc64. Fix buffer to
meet ppc64 alignment., 2017-07-28), adds an implementation for
__builtin___clear_cache on powerpc64, which was promptly ammended to
also be used with big endian mode in f67036b62c0c (This ppc64 implementation
of clear_cache works for both big and little endian., 2017-08-02)

clang will use this implementation for it's builtin on FreeBSD and result
in an abort() in the cases where 32-bit generation was requested (ex in
macppc or when the big endian powerpc64 build was done with "-m32") and as
reported[1] recently with pcre2, but there is no reason why the same code
couldn't be used in those cases, so use instead the more generic identifier
for the PowerPC architecture.

While at it, update the comment to reflect that POWER8/9 have a 128 byte
wide cache line and so the code could instead use 64 byte windows instead
but that possible optimization has been punted for now.

[1] https://github.com/PhilipHazel/pcre2/issues/92

Reviewed By: jhibbits, #powerpc, MaskRay

Differential Revision: https://reviews.llvm.org/D122640

(cherry picked from commit 81f5c6270cdfcdf80e6296df216b696a7a37c8b5)

Added: 
    

Modified: 
    compiler-rt/lib/builtins/clear_cache.c

Removed: 
    


################################################################################
diff  --git a/compiler-rt/lib/builtins/clear_cache.c b/compiler-rt/lib/builtins/clear_cache.c
index da0715914b416..1f1efbff3ab2a 100644
--- a/compiler-rt/lib/builtins/clear_cache.c
+++ b/compiler-rt/lib/builtins/clear_cache.c
@@ -130,7 +130,10 @@ void __clear_cache(void *start, void *end) {
     __asm __volatile("dsb ish");
   }
   __asm __volatile("isb sy");
-#elif defined(__powerpc64__)
+#elif defined(__powerpc__)
+  // Newer CPUs have a bigger line size made of multiple blocks, so the
+  // following value is a minimal common denominator for what used to be
+  // a single block cache line and is therefore inneficient.
   const size_t line_size = 32;
   const size_t len = (uintptr_t)end - (uintptr_t)start;