[llvm-branch-commits] [llvm] 474037d - Merging r370113:

Tom Stellard via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Wed Dec 4 13:59:09 PST 2019


Author: Luis Marques
Date: 2019-12-04T13:44:20-08:00
New Revision: 474037d798d21313864fd9d43ea93ac8be695c61

URL: https://github.com/llvm/llvm-project/commit/474037d798d21313864fd9d43ea93ac8be695c61
DIFF: https://github.com/llvm/llvm-project/commit/474037d798d21313864fd9d43ea93ac8be695c61.diff

LOG: Merging r370113:

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r370113 | luismarques | 2019-08-27 14:37:57 -0700 (Tue, 27 Aug 2019) | 5 lines

[RISCV] Implement RISCVRegisterInfo::getPointerRegClass

Fixes bug 43041

Differential Revision: https://reviews.llvm.org/D66752
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Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index 4f339475508f..56a50fe6ddc0 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -52,6 +52,12 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
   bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
     return true;
   }
+
+  const TargetRegisterClass *
+  getPointerRegClass(const MachineFunction &MF,
+                     unsigned Kind = 0) const override {
+    return &RISCV::GPRRegClass;
+  }
 };
 }
 


        


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