[llvm-branch-commits] [llvm-branch] r370438 - Merging r368164:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Aug 30 00:27:12 PDT 2019
Author: hans
Date: Fri Aug 30 00:27:12 2019
New Revision: 370438
URL: http://llvm.org/viewvc/llvm-project?rev=370438&view=rev
Log:
Merging r368164:
------------------------------------------------------------------------
r368164 | s.desmalen | 2019-08-07 14:41:38 +0200 (Wed, 07 Aug 2019) | 13 lines
[AArch64][WinCFI] Do not pair callee-save instructions in LoadStoreOptimizer
Prevent the LoadStoreOptimizer from pairing any load/store instructions with
instructions from the prologue/epilogue if the CFI information has encoded the
operations as separate instructions. This would otherwise lead to a mismatch
of the actual prologue size from the size as recorded in the Windows CFI.
Reviewers: efriedma, mstorsjo, ssijaric
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D65817
------------------------------------------------------------------------
Modified:
llvm/branches/release_90/ (props changed)
llvm/branches/release_90/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/branches/release_90/test/CodeGen/AArch64/wineh1.mir
llvm/branches/release_90/test/CodeGen/AArch64/wineh2.mir
llvm/branches/release_90/test/DebugInfo/COFF/AArch64/arm64-register-variables.ll
Propchange: llvm/branches/release_90/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Aug 30 00:27:12 2019
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,366431,366447,366481,366487,366527,366570,366660,366868,366925,367019,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367412,367417,367429,367580,367662,367750,367753,367846-367847,367898,367941,368004,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873,369011,369026,369084,369095,369097,369168,369199,369426,369443,369886,370036,370176,370204,370271
+/llvm/trunk:155241,366431,366447,366481,366487,366527,366570,366660,366868,366925,367019,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367412,367417,367429,367580,367662,367750,367753,367846-367847,367898,367941,368004,368164,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873,369011,369026,369084,369095,369097,369168,369199,369426,369443,369886,370036,370176,370204,370271
Modified: llvm/branches/release_90/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=370438&r1=370437&r2=370438&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/branches/release_90/lib/Target/AArch64/AArch64InstrInfo.cpp Fri Aug 30 00:27:12 2019
@@ -32,6 +32,7 @@
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/GlobalValue.h"
+#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Casting.h"
@@ -1928,6 +1929,17 @@ bool AArch64InstrInfo::isCandidateToMerg
if (isLdStPairSuppressed(MI))
return false;
+ // Do not pair any callee-save store/reload instructions in the
+ // prologue/epilogue if the CFI information encoded the operations as separate
+ // instructions, as that will cause the size of the actual prologue to mismatch
+ // with the prologue size recorded in the Windows CFI.
+ const MCAsmInfo *MAI = MI.getMF()->getTarget().getMCAsmInfo();
+ bool NeedsWinCFI = MAI->usesWindowsCFI() &&
+ MI.getMF()->getFunction().needsUnwindTableEntry();
+ if (NeedsWinCFI && (MI.getFlag(MachineInstr::FrameSetup) ||
+ MI.getFlag(MachineInstr::FrameDestroy)))
+ return false;
+
// On some CPUs quad load/store pairs are slower than two single load/stores.
if (Subtarget.isPaired128Slow()) {
switch (MI.getOpcode()) {
Modified: llvm/branches/release_90/test/CodeGen/AArch64/wineh1.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/AArch64/wineh1.mir?rev=370438&r1=370437&r2=370438&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/AArch64/wineh1.mir (original)
+++ llvm/branches/release_90/test/CodeGen/AArch64/wineh1.mir Fri Aug 30 00:27:12 2019
@@ -1,5 +1,7 @@
# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog -filetype=obj \
# RUN: | llvm-readobj --unwind | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -run-pass=aarch64-ldst-opt \
+# RUN: | FileCheck %s --check-prefix=CHECK-LDSTOPT
# This test case checks the basic validity of the .xdata section. It's
# documented at:
# https://docs.microsoft.com/en-us/cpp/build/arm64-exception-handling
@@ -7,7 +9,7 @@
# We expect to see the following in the .xdata section:
# CHECK: ExceptionData {
-# CHECK-NEXT: FunctionLength: 92
+# CHECK-NEXT: FunctionLength: 96
# CHECK-NEXT: Version: 0
# CHECK-NEXT: ExceptionData: No
# CHECK-NEXT: EpiloguePacked: No
@@ -24,7 +26,7 @@
# CHECK-NEXT: ]
# CHECK-NEXT: EpilogueScopes [
# CHECK-NEXT: EpilogueScope {
-# CHECK-NEXT: StartOffset: 15
+# CHECK-NEXT: StartOffset: 16
# CHECK-NEXT: EpilogueStartIndex: 13
# CHECK-NEXT: Opcodes [
# CHECK-NEXT: 0xc808 ; ldp x19, x20, [sp, #64]
@@ -39,6 +41,12 @@
# CHECK-NEXT: }
# CHECK-NEXT: ]
# CHECK-NEXT: }
+
+# Check that the load-store optimizer does not merge the two
+# callee-saved stores in the prologue.
+# CHECK-LDSTOPT: name: test
+# CHECK-LDSTOPT: frame-setup STRXui killed $x21, $sp, 6
+# CHECK-LDSTOPT: frame-setup STRXui killed $x22, $sp, 7
...
---
name: test
Modified: llvm/branches/release_90/test/CodeGen/AArch64/wineh2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/AArch64/wineh2.mir?rev=370438&r1=370437&r2=370438&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/AArch64/wineh2.mir (original)
+++ llvm/branches/release_90/test/CodeGen/AArch64/wineh2.mir Fri Aug 30 00:27:12 2019
@@ -3,7 +3,7 @@
# Test that the pre/post increment save of a flating point register is correct.
# CHECK: ExceptionData {
-# CHECK-NEXT: FunctionLength: 136
+# CHECK-NEXT: FunctionLength: 144
# CHECK-NEXT: Version: 0
# CHECK-NEXT: ExceptionData: No
# CHECK-NEXT: EpiloguePacked: No
@@ -23,7 +23,7 @@
# CHECK-NEXT: ]
# CHECK-NEXT: EpilogueScopes [
# CHECK-NEXT: EpilogueScope {
-# CHECK-NEXT: StartOffset: 25
+# CHECK-NEXT: StartOffset: 26
# CHECK-NEXT: EpilogueStartIndex: 19
# CHECK-NEXT: Opcodes [
# CHECK-NEXT: 0xc80e ; ldp x19, x20, [sp, #112]
Modified: llvm/branches/release_90/test/DebugInfo/COFF/AArch64/arm64-register-variables.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/DebugInfo/COFF/AArch64/arm64-register-variables.ll?rev=370438&r1=370437&r2=370438&view=diff
==============================================================================
--- llvm/branches/release_90/test/DebugInfo/COFF/AArch64/arm64-register-variables.ll (original)
+++ llvm/branches/release_90/test/DebugInfo/COFF/AArch64/arm64-register-variables.ll Fri Aug 30 00:27:12 2019
@@ -28,9 +28,9 @@
; OBJ: OffsetInParent: 0
; OBJ: BasePointerOffset: 12
; OBJ: LocalVariableAddrRange {
-; OBJ: OffsetStart: .text+0x10
+; OBJ: OffsetStart: .text+0x14
; OBJ: ISectStart: 0x0
-; OBJ: Range: 0x2C
+; OBJ: Range: 0x30
; OBJ: }
; OBJ: }
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