[llvm-branch-commits] [llvm-branch] r370063 - Merging r370036:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Tue Aug 27 07:30:02 2019
New Revision: 370063

URL: http://llvm.org/viewvc/llvm-project?rev=370063&view=rev
Log:
Merging r370036:
------------------------------------------------------------------------
r370036 | tnorthover | 2019-08-27 12:21:11 +0200 (Tue, 27 Aug 2019) | 8 lines

AArch64: avoid creating cycle in DAG for post-increment NEON ops.

Inserting a value into Visited has the effect of terminating a search for
predecessors if that node is seen. This is legitimate for the base address, and
acts as a slight performance optimization, but the vector-building node can be
paert of a legitimate cycle so we shouldn't stop searching there.

PR43056.
------------------------------------------------------------------------

Modified:
    llvm/branches/release_90/   (props changed)
    llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/branches/release_90/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll

Propchange: llvm/branches/release_90/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Aug 27 07:30:02 2019
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,366431,366447,366481,366487,366527,366570,366660,366868,366925,367019,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367412,367417,367429,367580,367662,367750,367753,367846-367847,367898,367941,368004,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873,369011,369026,369084,369095,369097,369168,369199,369426,369443
+/llvm/trunk:155241,366431,366447,366481,366487,366527,366570,366660,366868,366925,367019,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367412,367417,367429,367580,367662,367750,367753,367846-367847,367898,367941,368004,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873,369011,369026,369084,369095,369097,369168,369199,369426,369443,370036

Modified: llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=370063&r1=370062&r2=370063&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Aug 27 07:30:02 2019
@@ -10579,7 +10579,7 @@ static SDValue performPostLD1Combine(SDN
     // are predecessors to each other or the Vector.
     SmallPtrSet<const SDNode *, 32> Visited;
     SmallVector<const SDNode *, 16> Worklist;
-    Visited.insert(N);
+    Visited.insert(Addr.getNode());
     Worklist.push_back(User);
     Worklist.push_back(LD);
     Worklist.push_back(Vector.getNode());

Modified: llvm/branches/release_90/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll?rev=370063&r1=370062&r2=370063&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll (original)
+++ llvm/branches/release_90/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll Tue Aug 27 07:30:02 2019
@@ -6319,3 +6319,22 @@ define void  @test_ld1lane_build_i8(i8*
   store <8 x i8> %sub, <8 x i8>* %p
   ret void
 }
+
+define <4 x i32> @test_inc_cycle(<4 x i32> %vec, i32* %in) {
+; CHECK-LABEL: test_inc_cycle:
+; CHECK: ld1.s { v0 }[0], [x0]{{$}}
+
+  %elt = load i32, i32* %in
+  %newvec = insertelement <4 x i32> %vec, i32 %elt, i32 0
+
+  ; %inc cannot be %elt directly because we check that the load is only
+  ; used by the insert before trying to form post-inc.
+  %inc.vec = bitcast <4 x i32> %newvec to <2 x i64>
+  %inc = extractelement <2 x i64> %inc.vec, i32 0
+  %newaddr = getelementptr i32, i32* %in, i64 %inc
+  store i32* %newaddr, i32** @var
+
+  ret <4 x i32> %newvec
+}
+
+ at var = global i32* null