[llvm-branch-commits] [llvm-branch] r369651 - Merging r369095:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Aug 22 06:49:53 PDT 2019
Author: hans
Date: Thu Aug 22 06:49:53 2019
New Revision: 369651
URL: http://llvm.org/viewvc/llvm-project?rev=369651&view=rev
Log:
Merging r369095:
------------------------------------------------------------------------
r369095 | lewis-revill | 2019-08-16 12:28:34 +0200 (Fri, 16 Aug 2019) | 11 lines
[RISCV] Lower inline asm constraint A for RISC-V
This allows arguments with the constraint A to be lowered to input nodes
for RISC-V, which implies a memory address stored in a register.
This patch adds the minimal amount of code required to get operands with
the right constraints to compile.
https://reviews.llvm.org/D54296
------------------------------------------------------------------------
Modified:
llvm/branches/release_90/ (props changed)
llvm/branches/release_90/include/llvm/IR/InlineAsm.h
llvm/branches/release_90/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.h
llvm/branches/release_90/test/CodeGen/RISCV/inline-asm.ll
Propchange: llvm/branches/release_90/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Aug 22 06:49:53 2019
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,366431,366481,366487,366527,366570,366660,366868,366925,367019,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367412,367417,367429,367662,367750,367753,367846-367847,367898,367941,368004,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873,369011,369026,369084,369097,369168,369199
+/llvm/trunk:155241,366431,366481,366487,366527,366570,366660,366868,366925,367019,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367412,367417,367429,367662,367750,367753,367846-367847,367898,367941,368004,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873,369011,369026,369084,369095,369097,369168,369199
Modified: llvm/branches/release_90/include/llvm/IR/InlineAsm.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/include/llvm/IR/InlineAsm.h?rev=369651&r1=369650&r2=369651&view=diff
==============================================================================
--- llvm/branches/release_90/include/llvm/IR/InlineAsm.h (original)
+++ llvm/branches/release_90/include/llvm/IR/InlineAsm.h Thu Aug 22 06:49:53 2019
@@ -244,6 +244,7 @@ public:
Constraint_m,
Constraint_o,
Constraint_v,
+ Constraint_A,
Constraint_Q,
Constraint_R,
Constraint_S,
Modified: llvm/branches/release_90/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/RISCV/RISCVISelDAGToDAG.cpp?rev=369651&r1=369650&r2=369651&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (original)
+++ llvm/branches/release_90/lib/Target/RISCV/RISCVISelDAGToDAG.cpp Thu Aug 22 06:49:53 2019
@@ -179,6 +179,9 @@ bool RISCVDAGToDAGISel::SelectInlineAsmM
// operand and need no special handling.
OutOps.push_back(Op);
return false;
+ case InlineAsm::Constraint_A:
+ OutOps.push_back(Op);
+ return false;
default:
break;
}
Modified: llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp?rev=369651&r1=369650&r2=369651&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp Thu Aug 22 06:49:53 2019
@@ -2413,6 +2413,8 @@ RISCVTargetLowering::getConstraintType(S
case 'J':
case 'K':
return C_Immediate;
+ case 'A':
+ return C_Memory;
}
}
return TargetLowering::getConstraintType(Constraint);
@@ -2442,6 +2444,21 @@ RISCVTargetLowering::getRegForInlineAsmC
return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
}
+unsigned
+RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
+ // Currently only support length 1 constraints.
+ if (ConstraintCode.size() == 1) {
+ switch (ConstraintCode[0]) {
+ case 'A':
+ return InlineAsm::Constraint_A;
+ default:
+ break;
+ }
+ }
+
+ return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
+}
+
void RISCVTargetLowering::LowerAsmOperandForConstraint(
SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
SelectionDAG &DAG) const {
Modified: llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.h?rev=369651&r1=369650&r2=369651&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.h (original)
+++ llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.h Thu Aug 22 06:49:53 2019
@@ -93,6 +93,9 @@ public:
const char *getTargetNodeName(unsigned Opcode) const override;
ConstraintType getConstraintType(StringRef Constraint) const override;
+
+ unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
+
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override;
Modified: llvm/branches/release_90/test/CodeGen/RISCV/inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/RISCV/inline-asm.ll?rev=369651&r1=369650&r2=369651&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/RISCV/inline-asm.ll (original)
+++ llvm/branches/release_90/test/CodeGen/RISCV/inline-asm.ll Thu Aug 22 06:49:53 2019
@@ -150,6 +150,31 @@ define void @constraint_K() nounwind {
ret void
}
+define void @constraint_A(i8* %a) nounwind {
+; RV32I-LABEL: constraint_A:
+; RV32I: # %bb.0:
+; RV32I-NEXT: #APP
+; RV32I-NEXT: sb s0, 0(a0)
+; RV32I-NEXT: #NO_APP
+; RV32I-NEXT: #APP
+; RV32I-NEXT: lb s1, 0(a0)
+; RV32I-NEXT: #NO_APP
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: constraint_A:
+; RV64I: # %bb.0:
+; RV64I-NEXT: #APP
+; RV64I-NEXT: sb s0, 0(a0)
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: #APP
+; RV64I-NEXT: lb s1, 0(a0)
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ret
+ tail call void asm sideeffect "sb s0, $0", "*A"(i8* %a)
+ tail call void asm sideeffect "lb s1, $0", "*A"(i8* %a)
+ ret void
+}
+
define i32 @modifier_z_zero(i32 %a) nounwind {
; RV32I-LABEL: modifier_z_zero:
; RV32I: # %bb.0:
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