[llvm-branch-commits] [llvm-branch] r369086 - Merging r367019:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Aug 16 00:44:53 PDT 2019
Author: hans
Date: Fri Aug 16 00:44:53 2019
New Revision: 369086
URL: http://llvm.org/viewvc/llvm-project?rev=369086&view=rev
Log:
Merging r367019:
------------------------------------------------------------------------
r367019 | chill | 2019-07-25 15:56:04 +0200 (Thu, 25 Jul 2019) | 10 lines
[AArch64][SVE] Allow explicit size specifier for predicate operand
... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue
supporting the exsting behaviour of not requiring an explicit size
specifier. The preferred disasembly is *with* the specifier.
This is implemented by redefining intruction forms to require vector predicates
with explicit size and adding aliases, which allow a predicate with no size.
Differential Revision: https://reviews.llvm.org/D65145
------------------------------------------------------------------------
Modified:
llvm/branches/release_90/ (props changed)
llvm/branches/release_90/lib/Target/AArch64/SVEInstrFormats.td
llvm/branches/release_90/test/MC/AArch64/SVE/decp.s
llvm/branches/release_90/test/MC/AArch64/SVE/incp.s
llvm/branches/release_90/test/MC/AArch64/SVE/sqdecp.s
llvm/branches/release_90/test/MC/AArch64/SVE/sqincp.s
llvm/branches/release_90/test/MC/AArch64/SVE/uqdecp.s
llvm/branches/release_90/test/MC/AArch64/SVE/uqincp.s
Propchange: llvm/branches/release_90/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Aug 16 00:44:53 2019
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,366431,366481,366487,366527,366570,366660,366868,366925,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367417,367662,367750,367753,367846-367847,367898,367941,368004,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873
+/llvm/trunk:155241,366431,366481,366487,366527,366570,366660,366868,366925,367019,367030,367062,367084,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367417,367662,367750,367753,367846-367847,367898,367941,368004,368230,368300,368315,368324,368477-368478,368517-368519,368554,368572,368873
Modified: llvm/branches/release_90/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/AArch64/SVEInstrFormats.td?rev=369086&r1=369085&r2=369086&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/branches/release_90/lib/Target/AArch64/SVEInstrFormats.td Fri Aug 16 00:44:53 2019
@@ -403,12 +403,12 @@ multiclass sve_int_count_r_x64<bits<5> o
}
class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm,
- ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, PPRAny:$Pg),
- asm, "\t$Zdn, $Pg",
+ ZPRRegOp zprty, PPRRegOp pprty>
+: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, pprty:$Pm),
+ asm, "\t$Zdn, $Pm",
"",
[]>, Sched<[]> {
- bits<4> Pg;
+ bits<4> Pm;
bits<5> Zdn;
let Inst{31-24} = 0b00100101;
let Inst{23-22} = sz8_64;
@@ -416,7 +416,7 @@ class sve_int_count_v<bits<2> sz8_64, bi
let Inst{18-16} = opc{4-2};
let Inst{15-11} = 0b10000;
let Inst{10-9} = opc{1-0};
- let Inst{8-5} = Pg;
+ let Inst{8-5} = Pm;
let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn";
@@ -425,9 +425,16 @@ class sve_int_count_v<bits<2> sz8_64, bi
}
multiclass sve_int_count_v<bits<5> opc, string asm> {
- def _H : sve_int_count_v<0b01, opc, asm, ZPR16>;
- def _S : sve_int_count_v<0b10, opc, asm, ZPR32>;
- def _D : sve_int_count_v<0b11, opc, asm, ZPR64>;
+ def _H : sve_int_count_v<0b01, opc, asm, ZPR16, PPR16>;
+ def _S : sve_int_count_v<0b10, opc, asm, ZPR32, PPR32>;
+ def _D : sve_int_count_v<0b11, opc, asm, ZPR64, PPR64>;
+
+ def : InstAlias<asm # "\t$Zdn, $Pm",
+ (!cast<Instruction>(NAME # "_H") ZPR16:$Zdn, PPRAny:$Pm), 0>;
+ def : InstAlias<asm # "\t$Zdn, $Pm",
+ (!cast<Instruction>(NAME # "_S") ZPR32:$Zdn, PPRAny:$Pm), 0>;
+ def : InstAlias<asm # "\t$Zdn, $Pm",
+ (!cast<Instruction>(NAME # "_D") ZPR64:$Zdn, PPRAny:$Pm), 0>;
}
class sve_int_pcount_pred<bits<2> sz8_64, bits<4> opc, string asm,
Modified: llvm/branches/release_90/test/MC/AArch64/SVE/decp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/MC/AArch64/SVE/decp.s?rev=369086&r1=369085&r2=369086&view=diff
==============================================================================
--- llvm/branches/release_90/test/MC/AArch64/SVE/decp.s (original)
+++ llvm/branches/release_90/test/MC/AArch64/SVE/decp.s Fri Aug 16 00:44:53 2019
@@ -56,19 +56,37 @@ decp xzr, p15.d
// CHECK-UNKNOWN: ff 89 ed 25 <unknown>
decp z31.h, p15
-// CHECK-INST: decp z31.h, p15
+// CHECK-INST: decp z31.h, p15.h
+// CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 81 6d 25 <unknown>
+
+decp z31.h, p15.h
+// CHECK-INST: decp z31.h, p15.h
// CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 6d 25 <unknown>
decp z31.s, p15
-// CHECK-INST: decp z31.s, p15
+// CHECK-INST: decp z31.s, p15.s
+// CHECK-ENCODING: [0xff,0x81,0xad,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 81 ad 25 <unknown>
+
+decp z31.s, p15.s
+// CHECK-INST: decp z31.s, p15.s
// CHECK-ENCODING: [0xff,0x81,0xad,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ad 25 <unknown>
decp z31.d, p15
-// CHECK-INST: decp z31.d, p15
+// CHECK-INST: decp z31.d, p15.d
+// CHECK-ENCODING: [0xff,0x81,0xed,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 81 ed 25 <unknown>
+
+decp z31.d, p15.d
+// CHECK-INST: decp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xed,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ed 25 <unknown>
@@ -83,7 +101,7 @@ movprfx z31, z6
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
-decp z31.d, p15
+decp z31.d, p15.d
// CHECK-INST: decp z31.d, p15
// CHECK-ENCODING: [0xff,0x81,0xed,0x25]
// CHECK-ERROR: instruction requires: sve
Modified: llvm/branches/release_90/test/MC/AArch64/SVE/incp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/MC/AArch64/SVE/incp.s?rev=369086&r1=369085&r2=369086&view=diff
==============================================================================
--- llvm/branches/release_90/test/MC/AArch64/SVE/incp.s (original)
+++ llvm/branches/release_90/test/MC/AArch64/SVE/incp.s Fri Aug 16 00:44:53 2019
@@ -56,19 +56,37 @@ incp xzr, p15.d
// CHECK-UNKNOWN: ff 89 ec 25 <unknown>
incp z31.h, p15
-// CHECK-INST: incp z31.h, p15
+// CHECK-INST: incp z31.h, p15.h
+// CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 81 6c 25 <unknown>
+
+incp z31.h, p15.h
+// CHECK-INST: incp z31.h, p15.h
// CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 6c 25 <unknown>
incp z31.s, p15
-// CHECK-INST: incp z31.s, p15
+// CHECK-INST: incp z31.s, p15.s
+// CHECK-ENCODING: [0xff,0x81,0xac,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 81 ac 25 <unknown>
+
+incp z31.s, p15.s
+// CHECK-INST: incp z31.s, p15.s
// CHECK-ENCODING: [0xff,0x81,0xac,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ac 25 <unknown>
incp z31.d, p15
-// CHECK-INST: incp z31.d, p15
+// CHECK-INST: incp z31.d, p15.d
+// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 81 ec 25 <unknown>
+
+incp z31.d, p15.d
+// CHECK-INST: incp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ec 25 <unknown>
@@ -83,8 +101,8 @@ movprfx z31, z6
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown>
-incp z31.d, p15
-// CHECK-INST: incp z31.d, p15
+incp z31.d, p15.d
+// CHECK-INST: incp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ec 25 <unknown>
Modified: llvm/branches/release_90/test/MC/AArch64/SVE/sqdecp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/MC/AArch64/SVE/sqdecp.s?rev=369086&r1=369085&r2=369086&view=diff
==============================================================================
--- llvm/branches/release_90/test/MC/AArch64/SVE/sqdecp.s (original)
+++ llvm/branches/release_90/test/MC/AArch64/SVE/sqdecp.s Fri Aug 16 00:44:53 2019
@@ -56,19 +56,37 @@ sqdecp xzr, p15.d, wzr
// CHECK-UNKNOWN: ff 89 ea 25 <unknown>
sqdecp z0.h, p0
-// CHECK-INST: sqdecp z0.h, p0
+// CHECK-INST: sqdecp z0.h, p0.h
+// CHECK-ENCODING: [0x00,0x80,0x6a,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 6a 25 <unknown>
+
+sqdecp z0.h, p0.h
+// CHECK-INST: sqdecp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x6a,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 6a 25 <unknown>
sqdecp z0.s, p0
-// CHECK-INST: sqdecp z0.s, p0
+// CHECK-INST: sqdecp z0.s, p0.s
+// CHECK-ENCODING: [0x00,0x80,0xaa,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 aa 25 <unknown>
+
+sqdecp z0.s, p0.s
+// CHECK-INST: sqdecp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xaa,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 aa 25 <unknown>
sqdecp z0.d, p0
-// CHECK-INST: sqdecp z0.d, p0
+// CHECK-INST: sqdecp z0.d, p0.d
+// CHECK-ENCODING: [0x00,0x80,0xea,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 ea 25 <unknown>
+
+sqdecp z0.d, p0.d
+// CHECK-INST: sqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xea,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ea 25 <unknown>
@@ -83,8 +101,8 @@ movprfx z0, z7
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
-sqdecp z0.d, p0
-// CHECK-INST: sqdecp z0.d, p0
+sqdecp z0.d, p0.d
+// CHECK-INST: sqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xea,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ea 25 <unknown>
Modified: llvm/branches/release_90/test/MC/AArch64/SVE/sqincp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/MC/AArch64/SVE/sqincp.s?rev=369086&r1=369085&r2=369086&view=diff
==============================================================================
--- llvm/branches/release_90/test/MC/AArch64/SVE/sqincp.s (original)
+++ llvm/branches/release_90/test/MC/AArch64/SVE/sqincp.s Fri Aug 16 00:44:53 2019
@@ -56,19 +56,37 @@ sqincp xzr, p15.d, wzr
// CHECK-UNKNOWN: ff 89 e8 25 <unknown>
sqincp z0.h, p0
-// CHECK-INST: sqincp z0.h, p0
+// CHECK-INST: sqincp z0.h, p0.h
+// CHECK-ENCODING: [0x00,0x80,0x68,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 68 25 <unknown>
+
+sqincp z0.h, p0.h
+// CHECK-INST: sqincp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x68,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 68 25 <unknown>
sqincp z0.s, p0
-// CHECK-INST: sqincp z0.s, p0
+// CHECK-INST: sqincp z0.s, p0.s
+// CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 a8 25 <unknown>
+
+sqincp z0.s, p0.s
+// CHECK-INST: sqincp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a8 25 <unknown>
sqincp z0.d, p0
-// CHECK-INST: sqincp z0.d, p0
+// CHECK-INST: sqincp z0.d, p0.d
+// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 e8 25 <unknown>
+
+sqincp z0.d, p0.d
+// CHECK-INST: sqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e8 25 <unknown>
@@ -83,8 +101,8 @@ movprfx z0, z7
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
-sqincp z0.d, p0
-// CHECK-INST: sqincp z0.d, p0
+sqincp z0.d, p0.d
+// CHECK-INST: sqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e8 25 <unknown>
Modified: llvm/branches/release_90/test/MC/AArch64/SVE/uqdecp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/MC/AArch64/SVE/uqdecp.s?rev=369086&r1=369085&r2=369086&view=diff
==============================================================================
--- llvm/branches/release_90/test/MC/AArch64/SVE/uqdecp.s (original)
+++ llvm/branches/release_90/test/MC/AArch64/SVE/uqdecp.s Fri Aug 16 00:44:53 2019
@@ -56,19 +56,37 @@ uqdecp wzr, p15.d
// CHECK-UNKNOWN: ff 89 eb 25 <unknown>
uqdecp z0.h, p0
-// CHECK-INST: uqdecp z0.h, p0
+// CHECK-INST: uqdecp z0.h, p0.h
+// CHECK-ENCODING: [0x00,0x80,0x6b,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 6b 25 <unknown>
+
+uqdecp z0.h, p0.h
+// CHECK-INST: uqdecp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x6b,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 6b 25 <unknown>
uqdecp z0.s, p0
-// CHECK-INST: uqdecp z0.s, p0
+// CHECK-INST: uqdecp z0.s, p0.s
+// CHECK-ENCODING: [0x00,0x80,0xab,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 ab 25 <unknown>
+
+uqdecp z0.s, p0.s
+// CHECK-INST: uqdecp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xab,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ab 25 <unknown>
uqdecp z0.d, p0
-// CHECK-INST: uqdecp z0.d, p0
+// CHECK-INST: uqdecp z0.d, p0.d
+// CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 eb 25 <unknown>
+
+uqdecp z0.d, p0.d
+// CHECK-INST: uqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 eb 25 <unknown>
@@ -83,8 +101,8 @@ movprfx z0, z7
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
-uqdecp z0.d, p0
-// CHECK-INST: uqdecp z0.d, p0
+uqdecp z0.d, p0.d
+// CHECK-INST: uqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 eb 25 <unknown>
Modified: llvm/branches/release_90/test/MC/AArch64/SVE/uqincp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/MC/AArch64/SVE/uqincp.s?rev=369086&r1=369085&r2=369086&view=diff
==============================================================================
--- llvm/branches/release_90/test/MC/AArch64/SVE/uqincp.s (original)
+++ llvm/branches/release_90/test/MC/AArch64/SVE/uqincp.s Fri Aug 16 00:44:53 2019
@@ -56,19 +56,37 @@ uqincp wzr, p15.d
// CHECK-UNKNOWN: ff 89 e9 25 <unknown>
uqincp z0.h, p0
-// CHECK-INST: uqincp z0.h, p0
+// CHECK-INST: uqincp z0.h, p0.h
+// CHECK-ENCODING: [0x00,0x80,0x69,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 69 25 <unknown>
+
+uqincp z0.h, p0.h
+// CHECK-INST: uqincp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x69,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 69 25 <unknown>
uqincp z0.s, p0
-// CHECK-INST: uqincp z0.s, p0
+// CHECK-INST: uqincp z0.s, p0.s
+// CHECK-ENCODING: [0x00,0x80,0xa9,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 a9 25 <unknown>
+
+uqincp z0.s, p0.s
+// CHECK-INST: uqincp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xa9,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a9 25 <unknown>
uqincp z0.d, p0
-// CHECK-INST: uqincp z0.d, p0
+// CHECK-INST: uqincp z0.d, p0.d
+// CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 e9 25 <unknown>
+
+uqincp z0.d, p0.d
+// CHECK-INST: uqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e9 25 <unknown>
@@ -83,8 +101,8 @@ movprfx z0, z7
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
-uqincp z0.d, p0
-// CHECK-INST: uqincp z0.d, p0
+uqincp z0.d, p0.d
+// CHECK-INST: uqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e9 25 <unknown>
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