[llvm-branch-commits] [llvm-branch] r223014 - Merged from r217436:
Daniel Sanders
daniel.sanders at imgtec.com
Mon Dec 1 05:17:00 PST 2014
Author: dsanders
Date: Mon Dec 1 07:17:00 2014
New Revision: 223014
URL: http://llvm.org/viewvc/llvm-project?rev=223014&view=rev
Log:
Merged from r217436:
[mips] Move MipsTargetLowering::MipsCC::regSize() to MipsSubtarget::getGPRSizeInBytes()
Summary:
The GPR size is more a property of the subtarget than that of the ABI so move
this information to the MipsSubtarget.
No functional change.
Reviewers: vmedic
Reviewed By: vmedic
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5009
Modified:
llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp
llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h
llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h
Modified: llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp?rev=223014&r1=223013&r2=223014&view=diff
==============================================================================
--- llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.cpp Mon Dec 1 07:17:00 2014
@@ -3508,17 +3508,18 @@ void MipsTargetLowering::MipsCC::handleB
assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
struct ByValArgInfo ByVal;
- unsigned RegSize = regSize();
- unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
- unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
- RegSize * 2);
+ unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
+ unsigned ByValSize =
+ RoundUpToAlignment(ArgFlags.getByValSize(), RegSizeInBytes);
+ unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSizeInBytes),
+ RegSizeInBytes * 2);
if (useRegsForByval())
allocateRegs(ByVal, ByValSize, Align);
// Allocate space on caller's stack.
- ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
- Align);
+ ByVal.Address =
+ CCInfo.AllocateStack(ByValSize - RegSizeInBytes * ByVal.NumRegs, Align);
CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
LocInfo));
ByValArgs.push_back(ByVal);
@@ -3561,23 +3562,24 @@ const MCPhysReg *MipsTargetLowering::Mip
void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
unsigned ByValSize,
unsigned Align) {
- unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
+ unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
+ unsigned NumIntArgRegs = numIntArgRegs();
const MCPhysReg *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
- assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
+ assert(!(ByValSize % RegSizeInBytes) && !(Align % RegSizeInBytes) &&
"Byval argument's size and alignment should be a multiple of"
- "RegSize.");
+ "RegSizeInBytes.");
ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
- // If Align > RegSize, the first arg register must be even.
- if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
+ // If Align > RegSizeInBytes, the first arg register must be even.
+ if ((Align > RegSizeInBytes) && (ByVal.FirstIdx % 2)) {
CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
++ByVal.FirstIdx;
}
// Mark the registers allocated.
for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
- ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
+ ByValSize -= RegSizeInBytes, ++I, ++ByVal.NumRegs)
CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
}
@@ -3596,10 +3598,6 @@ MVT MipsTargetLowering::MipsCC::getRegVT
return VT;
}
-unsigned MipsTargetLowering::MipsCC::regSize() const {
- return Subtarget.isGP32bit() ? 4 : 8;
-}
-
void MipsTargetLowering::
copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
@@ -3607,13 +3605,15 @@ copyByValRegs(SDValue Chain, SDLoc DL, s
const MipsCC &CC, const ByValArgInfo &ByVal) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
- unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
+ unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
+ unsigned RegAreaSize = ByVal.NumRegs * GPRSizeInBytes;
unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
int FrameObjOffset;
if (RegAreaSize)
- FrameObjOffset = (int)CC.reservedArgArea() -
- (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
+ FrameObjOffset =
+ (int)CC.reservedArgArea() -
+ (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * GPRSizeInBytes);
else
FrameObjOffset = ByVal.Address;
@@ -3627,13 +3627,13 @@ copyByValRegs(SDValue Chain, SDLoc DL, s
return;
// Copy arg registers.
- MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
+ MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
const TargetRegisterClass *RC = getRegClassFor(RegTy);
for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
unsigned VReg = addLiveIn(MF, ArgReg, RC);
- unsigned Offset = I * CC.regSize();
+ unsigned Offset = I * GPRSizeInBytes;
SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
DAG.getConstant(Offset, PtrTy));
SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
@@ -3653,7 +3653,7 @@ passByValArg(SDValue Chain, SDLoc DL,
const ISD::ArgFlagsTy &Flags, bool isLittle) const {
unsigned ByValSizeInBytes = Flags.getByValSize();
unsigned OffsetInBytes = 0; // From beginning of struct
- unsigned RegSizeInBytes = CC.regSize();
+ unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
@@ -3747,8 +3747,8 @@ void MipsTargetLowering::writeVarArgRegs
const MCPhysReg *ArgRegs = CC.intArgRegs();
const CCState &CCInfo = CC.getCCInfo();
unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
- unsigned RegSize = CC.regSize();
- MVT RegTy = MVT::getIntegerVT(RegSize * 8);
+ unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
+ MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
const TargetRegisterClass *RC = getRegClassFor(RegTy);
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
@@ -3758,23 +3758,25 @@ void MipsTargetLowering::writeVarArgRegs
int VaArgOffset;
if (NumRegs == Idx)
- VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
+ VaArgOffset =
+ RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSizeInBytes);
else
- VaArgOffset = (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
+ VaArgOffset =
+ (int)CC.reservedArgArea() - (int)(RegSizeInBytes * (NumRegs - Idx));
// Record the frame index of the first variable argument
// which is a value necessary to VASTART.
- int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
+ int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
MipsFI->setVarArgsFrameIndex(FI);
// Copy the integer registers that have not been used for argument passing
// to the argument register save area. For O32, the save area is allocated
// in the caller's stack frame, while for N32/64, it is allocated in the
// callee's stack frame.
- for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
+ for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSizeInBytes) {
unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
- FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
+ FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
MachinePointerInfo(), false, false, 0);
Modified: llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h?rev=223014&r1=223013&r2=223014&view=diff
==============================================================================
--- llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/branches/release_35/lib/Target/Mips/MipsISelLowering.h Mon Dec 1 07:17:00 2014
@@ -379,9 +379,6 @@ namespace llvm {
/// hasByValArg - Returns true if function has byval arguments.
bool hasByValArg() const { return !ByValArgs.empty(); }
- /// regSize - Size (in number of bits) of integer registers.
- unsigned regSize() const;
-
/// numIntArgRegs - Number of integer registers available for calls.
unsigned numIntArgRegs() const;
Modified: llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h?rev=223014&r1=223013&r2=223014&view=diff
==============================================================================
--- llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/branches/release_35/lib/Target/Mips/MipsSubtarget.h Mon Dec 1 07:17:00 2014
@@ -212,6 +212,7 @@ public:
bool isNotFP64bit() const { return !IsFP64bit; }
bool isGP64bit() const { return IsGP64bit; }
bool isGP32bit() const { return !IsGP64bit; }
+ unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
bool isSingleFloat() const { return IsSingleFloat; }
bool isNotSingleFloat() const { return !IsSingleFloat; }
bool hasVFPU() const { return HasVFPU; }
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