[Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

Jaydeep Patil via lldb-commits lldb-commits at lists.llvm.org
Mon Aug 17 04:13:03 PDT 2015

jaydeep created this revision.
jaydeep added a reviewer: clayborg.
jaydeep added subscribers: lldb-commits, bhushan, sagar, mohit.bhakkad, nitesh.jain.
jaydeep set the repository for this revision to rL LLVM.

This patch enables setting of breakpoints and disassembly for microMIPS applications running on bare-iron targets like IASim.

MIPS uses bit #0 (ISA bit) of an address for ISA mode (1 for microMIPS/MIPS16 and 0 for MIPS). The resulting address is called as compressed address when ISA bit is set. This allows processor to switch between microMIPS and MIPS without any need for special mode-control register. This bit is then cleared by the processor while fetching the instruction from memory. However, apart from .debug_line, none of the ELF/DWARF sections set the ISA bit. 

In this patch:
1)	The symbol table is recorded in the form of compressed address for microMIPS symbols, so that corresponding debug_line can be decoded properly.
2)	Memory read/write of compressed address has been handled




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