[clang] [llvm] [RISCV][MC] Add experimental Smip, and Ssip support (PR #215095)

[Zeyi Xu via cfe-commits]

zeyi2 wrote:

> I think maybe the way forward is to add only the assembly info, and leave out the codegen info (i.e. `mayLoad`, `Uses`, `Defs`, `isBarrier`, `isReturn`, `isTerminator`), which we can come back to when we implement code generation for these instructions.

That makes sense. I've removed these properties, leaving only the instruction encodings and assembler predicates for now. Thanks!

https://github.com/llvm/llvm-project/pull/215095