[clang] [llvm] [RISCV][MC] Add experimental Smip, and Ssip support (PR #215095)
Zeyi Xu via cfe-commits
cfe-commits at lists.llvm.org
Tue Aug 11 03:10:33 PDT 2026
https://github.com/zeyi2 updated https://github.com/llvm/llvm-project/pull/215095
>From 85dec3bf2d0f30e8a04d1799b33c69f3ac75a221 Mon Sep 17 00:00:00 2001
From: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: Sun, 9 Aug 2026 21:36:33 +0800
Subject: [PATCH 1/3] [RISCV][MC] Add experimental Smeihv, Sseihv, Smip, and
Ssip support
---
.../Driver/print-supported-extensions-riscv.c | 4 +++
.../test/Preprocessor/riscv-target-features.c | 36 +++++++++++++++++++
llvm/docs/RISCVUsage.rst | 2 +-
llvm/docs/ReleaseNotes.md | 4 +++
llvm/lib/Target/RISCV/RISCVFeatures.td | 22 ++++++++++++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td | 24 +++++++++++++
llvm/test/CodeGen/RISCV/attributes.ll | 16 +++++++++
llvm/test/CodeGen/RISCV/features-info.ll | 4 +++
llvm/test/MC/RISCV/attribute-arch.s | 12 +++++++
llvm/test/MC/RISCV/smip-ssip-invalid.s | 33 +++++++++++++++++
llvm/test/MC/RISCV/smip-valid.s | 18 ++++++++++
llvm/test/MC/RISCV/ssip-valid.s | 18 ++++++++++
.../TargetParser/RISCVISAInfoTest.cpp | 4 +++
14 files changed, 197 insertions(+), 1 deletion(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td
create mode 100644 llvm/test/MC/RISCV/smip-ssip-invalid.s
create mode 100644 llvm/test/MC/RISCV/smip-valid.s
create mode 100644 llvm/test/MC/RISCV/ssip-valid.s
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index f90a5fc581baa..7ab9adcb4b44a 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -272,11 +272,15 @@
// CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data)
// CHECK-NEXT: smcsps 0.19 'Smcsps' (Conditional Stack Pointer Swap at Machine Level)
// CHECK-NEXT: smehv 0.19 'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level)
+// CHECK-NEXT: smeihv 0.19 'Smeihv' (External Interrupt Hardware Vectoring at Machine Level)
// CHECK-NEXT: smijt 0.19 'Smijt' (Interrupt Jump Table at Machine Level)
+// CHECK-NEXT: smip 0.19 'Smip' (Support for Interrupt Handler Push/Pop at Machine Level)
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
// CHECK-NEXT: sscsps 0.19 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level)
// CHECK-NEXT: ssehv 0.19 'Ssehv' (Synchronous Exception Hardware Vectoring at Supervisor Level)
+// CHECK-NEXT: sseihv 0.19 'Sseihv' (External Interrupt Hardware Vectoring at Supervisor Level)
// CHECK-NEXT: ssijt 0.19 'Ssijt' (Interrupt Jump Table at Supervisor Level)
+// CHECK-NEXT: ssip 0.19 'Ssip' (Support for Interrupt Handler Push/Pop at Supervisor Level)
// CHECK-NEXT: svukte 1.0 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
// CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump)
// CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 752e9702d9388..e95698c88734f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -39,8 +39,10 @@
// CHECK-NOT: __riscv_smctr{{.*$}}
// CHECK-NOT: __riscv_smdbltrp {{.*$}}
// CHECK-NOT: __riscv_smehv {{.*$}}
+// CHECK-NOT: __riscv_smeihv {{.*$}}
// CHECK-NOT: __riscv_smepmp {{.*$}}
// CHECK-NOT: __riscv_smijt {{.*$}}
+// CHECK-NOT: __riscv_smip {{.*$}}
// CHECK-NOT: __riscv_smmpm{{.*$}}
// CHECK-NOT: __riscv_smnpm{{.*$}}
// CHECK-NOT: __riscv_smpmpmt {{.*$}}
@@ -56,7 +58,9 @@
// CHECK-NOT: __riscv_ssctr{{.*$}}
// CHECK-NOT: __riscv_ssdbltrp {{.*$}}
// CHECK-NOT: __riscv_ssehv {{.*$}}
+// CHECK-NOT: __riscv_sseihv {{.*$}}
// CHECK-NOT: __riscv_ssijt {{.*$}}
+// CHECK-NOT: __riscv_ssip {{.*$}}
// CHECK-NOT: __riscv_ssnpm{{.*$}}
// CHECK-NOT: __riscv_sspm{{.*$}}
// CHECK-NOT: __riscv_ssqosid{{.*$}}
@@ -1445,6 +1449,38 @@
// CHECK-SSEHV-EXT: __riscv_ssehv 19000{{$}}
// CHECK-SSEHV-EXT: __riscv_ssijt 19000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_smeihv0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMEIHV-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_smeihv0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMEIHV-EXT %s
+// CHECK-SMEIHV-EXT: __riscv_smeihv 19000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_sseihv0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSEIHV-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_sseihv0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSEIHV-EXT %s
+// CHECK-SSEIHV-EXT: __riscv_sseihv 19000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_smip0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMIP-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_smip0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMIP-EXT %s
+// CHECK-SMIP-EXT: __riscv_smip 19000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_ssip0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSIP-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_ssip0p19 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSIP-EXT %s
+// CHECK-SSIP-EXT: __riscv_ssip 19000{{$}}
+
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32ismpmpmt0p6 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMPMPMT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8fbe60c55d64c..484cc1ef5a7aa 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -347,7 +347,7 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zicfilp``, ``experimental-zicfiss``
LLVM implements the `1.0 release specification <https://github.com/riscv/riscv-cfi/releases/tag/v1.0>`__.
-``experimental-smcsps``, ``experimental-sscsps``, ``experimental-smijt``, ``experimental-ssijt``, ``experimental-smehv``, ``experimental-ssehv``
+``experimental-smcsps``, ``experimental-sscsps``, ``experimental-smijt``, ``experimental-ssijt``, ``experimental-smehv``, ``experimental-ssehv``, ``experimental-smeihv``, ``experimental-sseihv``, ``experimental-smip``, ``experimental-ssip``
LLVM implements the `0.19 release specification <https://github.com/riscv/riscv-fast-interrupt/releases/tag/v0.19>`__.
``experimental-zvbc32e``, ``experimental-zvkgs``
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index efd33a907cfa7..e4d72d2234cbd 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -102,6 +102,10 @@ Makes programs 10x faster by doing Special New Thing.
table extensions and the `Smehv` and `Ssehv` synchronous exception hardware
vectoring extensions.
+* Added experimental MC support for the `Smeihv` and `Sseihv` external
+ interrupt hardware vectoring extensions and the `Smip` and `Ssip` interrupt
+ handler push/pop extensions.
+
* Bump Svukte extension to 1.0.
### Changes to the WebAssembly Backend
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 4e9710e2ecb7e..2221f23dda11f 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1115,6 +1115,28 @@ def FeatureStdExtSsehv
"Synchronous Exception Hardware Vectoring at Supervisor Level",
[FeatureStdExtSsijt]>;
+def FeatureStdExtSmeihv
+ : RISCVExperimentalExtension<0, 19,
+ "External Interrupt Hardware Vectoring at Machine Level">;
+def FeatureStdExtSseihv
+ : RISCVExperimentalExtension<0, 19,
+ "External Interrupt Hardware Vectoring at Supervisor Level">;
+
+def FeatureStdExtSmip
+ : RISCVExperimentalExtension<0, 19,
+ "Support for Interrupt Handler Push/Pop at Machine Level">;
+def HasStdExtSmip : Predicate<"Subtarget->hasStdExtSmip()">,
+ AssemblerPredicate<(all_of FeatureStdExtSmip),
+ "'Smip' (Support for Interrupt Handler Push/Pop at "
+ "Machine Level)">;
+def FeatureStdExtSsip
+ : RISCVExperimentalExtension<0, 19,
+ "Support for Interrupt Handler Push/Pop at Supervisor Level">;
+def HasStdExtSsip : Predicate<"Subtarget->hasStdExtSsip()">,
+ AssemblerPredicate<(all_of FeatureStdExtSsip),
+ "'Ssip' (Support for Interrupt Handler Push/Pop at "
+ "Supervisor Level)">;
+
def FeatureStdExtSmpmpmt
: RISCVExperimentalExtension<0, 6, "PMP-based Memory Types Extension">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 5d93509477102..b4b1bc9573b41 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2400,6 +2400,7 @@ include "RISCVInstrInfoZilx.td"
// Privileged
include "RISCVInstrInfoSmcsps.td"
+include "RISCVInstrInfoSmip.td"
// Scalar FP
include "RISCVInstrInfoF.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td b/llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td
new file mode 100644
index 0000000000000..29baca4848a53
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td
@@ -0,0 +1,24 @@
+//===-- RISCVInstrInfoSmip.td ------------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+let mayLoad = 1, Uses = [X2], Defs = [X2, X10, X11, X12, X13, X14, X15],
+ isBarrier = 1, isReturn = 1, isTerminator = 1 in {
+let Predicates = [HasStdExtSmip] in
+def MIPOPRET : Priv<"mipopret", 0b0011000>, Sched<[]> {
+ let rd = 0;
+ let rs1 = 0;
+ let rs2 = 0b01000;
+}
+
+let Predicates = [HasStdExtSsip] in
+def SIPOPRET : Priv<"sipopret", 0b0001000>, Sched<[]> {
+ let rd = 0;
+ let rs1 = 0;
+ let rs2 = 0b01000;
+}
+} // isBarrier = 1, isReturn = 1, isTerminator = 1
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index df521014e3d16..363b78e1e46b8 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -135,6 +135,10 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssijt %s -o - | FileCheck --check-prefix=RV32SSIJT %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smehv %s -o - | FileCheck --check-prefix=RV32SMEHV %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssehv %s -o - | FileCheck --check-prefix=RV32SSEHV %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-smeihv %s -o - | FileCheck --check-prefix=RV32SMEIHV %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-sseihv %s -o - | FileCheck --check-prefix=RV32SSEIHV %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-smip %s -o - | FileCheck --check-prefix=RV32SMIP %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssip %s -o - | FileCheck --check-prefix=RV32SSIP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SMPMPMT %s
; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s
; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
@@ -308,6 +312,10 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssijt %s -o - | FileCheck --check-prefix=RV64SSIJT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smehv %s -o - | FileCheck --check-prefix=RV64SMEHV %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssehv %s -o - | FileCheck --check-prefix=RV64SSEHV %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-smeihv %s -o - | FileCheck --check-prefix=RV64SMEIHV %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-sseihv %s -o - | FileCheck --check-prefix=RV64SSEIHV %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-smip %s -o - | FileCheck --check-prefix=RV64SMIP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssip %s -o - | FileCheck --check-prefix=RV64SSIP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SMPMPMT %s
; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s
; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
@@ -491,6 +499,10 @@
; RV32SSIJT: .attribute 5, "rv32i2p1_ssijt0p19"
; RV32SMEHV: .attribute 5, "rv32i2p1_smehv0p19_smijt0p19"
; RV32SSEHV: .attribute 5, "rv32i2p1_ssehv0p19_ssijt0p19"
+; RV32SMEIHV: .attribute 5, "rv32i2p1_smeihv0p19"
+; RV32SSEIHV: .attribute 5, "rv32i2p1_sseihv0p19"
+; RV32SMIP: .attribute 5, "rv32i2p1_smip0p19"
+; RV32SSIP: .attribute 5, "rv32i2p1_ssip0p19"
; RV32SMPMPMT: .attribute 5, "rv32i2p1_smpmpmt0p6"
; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
@@ -661,6 +673,10 @@
; RV64SSIJT: .attribute 5, "rv64i2p1_ssijt0p19"
; RV64SMEHV: .attribute 5, "rv64i2p1_smehv0p19_smijt0p19"
; RV64SSEHV: .attribute 5, "rv64i2p1_ssehv0p19_ssijt0p19"
+; RV64SMEIHV: .attribute 5, "rv64i2p1_smeihv0p19"
+; RV64SSEIHV: .attribute 5, "rv64i2p1_sseihv0p19"
+; RV64SMIP: .attribute 5, "rv64i2p1_smip0p19"
+; RV64SSIP: .attribute 5, "rv64i2p1_ssip0p19"
; RV64SMPMPMT: .attribute 5, "rv64i2p1_smpmpmt0p6"
; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index febe312db5836..c08d5db853853 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -26,11 +26,15 @@
; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
; CHECK-NEXT: experimental-smcsps - 'Smcsps' (Conditional Stack Pointer Swap at Machine Level).
; CHECK-NEXT: experimental-smehv - 'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level).
+; CHECK-NEXT: experimental-smeihv - 'Smeihv' (External Interrupt Hardware Vectoring at Machine Level).
; CHECK-NEXT: experimental-smijt - 'Smijt' (Interrupt Jump Table at Machine Level).
+; CHECK-NEXT: experimental-smip - 'Smip' (Support for Interrupt Handler Push/Pop at Machine Level).
; CHECK-NEXT: experimental-smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension).
; CHECK-NEXT: experimental-sscsps - 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level).
; CHECK-NEXT: experimental-ssehv - 'Ssehv' (Synchronous Exception Hardware Vectoring at Supervisor Level).
+; CHECK-NEXT: experimental-sseihv - 'Sseihv' (External Interrupt Hardware Vectoring at Supervisor Level).
; CHECK-NEXT: experimental-ssijt - 'Ssijt' (Interrupt Jump Table at Supervisor Level).
+; CHECK-NEXT: experimental-ssip - 'Ssip' (Support for Interrupt Handler Push/Pop at Supervisor Level).
; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).
; CHECK-NEXT: experimental-xqccmt - 'Xqccmt' (Qualcomm 16-bit Table Jump).
; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs).
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index bf792bf4d2e54..5d39ee3c8ccd4 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -375,6 +375,18 @@
.attribute arch, "rv32i_ssehv0p19"
# CHECK: attribute 5, "rv32i2p1_ssehv0p19_ssijt0p19"
+.attribute arch, "rv32i_smeihv0p19"
+# CHECK: attribute 5, "rv32i2p1_smeihv0p19"
+
+.attribute arch, "rv32i_sseihv0p19"
+# CHECK: attribute 5, "rv32i2p1_sseihv0p19"
+
+.attribute arch, "rv32i_smip0p19"
+# CHECK: attribute 5, "rv32i2p1_smip0p19"
+
+.attribute arch, "rv32i_ssip0p19"
+# CHECK: attribute 5, "rv32i2p1_ssip0p19"
+
.attribute arch, "rv32i_smpmpmt0p6"
# CHECK: attribute 5, "rv32i2p1_smpmpmt0p6"
diff --git a/llvm/test/MC/RISCV/smip-ssip-invalid.s b/llvm/test/MC/RISCV/smip-ssip-invalid.s
new file mode 100644
index 0000000000000..0f2953cf93830
--- /dev/null
+++ b/llvm/test/MC/RISCV/smip-ssip-invalid.s
@@ -0,0 +1,33 @@
+# RUN: split-file %s %t
+# RUN: not llvm-mc -triple=riscv32 %t/no-features.s 2>&1 \
+# RUN: | FileCheck --check-prefix=NO-FEATURES %t/no-features.s
+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-smip \
+# RUN: %t/no-ssip.s 2>&1 \
+# RUN: | FileCheck --check-prefix=NO-SSIP %t/no-ssip.s
+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-ssip \
+# RUN: %t/no-smip.s 2>&1 \
+# RUN: | FileCheck --check-prefix=NO-SMIP %t/no-smip.s
+# RUN: not llvm-mc -triple=riscv32 \
+# RUN: -mattr=+experimental-smip,+experimental-ssip \
+# RUN: %t/invalid-operands.s 2>&1 \
+# RUN: | FileCheck --check-prefix=INVALID-OPERANDS %t/invalid-operands.s
+
+#--- no-features.s
+mipopret
+# NO-FEATURES: :[[#@LINE-1]]:1: error: instruction requires the following: 'Smip'
+sipopret
+# NO-FEATURES: :[[#@LINE-1]]:1: error: instruction requires the following: 'Ssip'
+
+#--- no-ssip.s
+sipopret
+# NO-SSIP: :[[#@LINE-1]]:1: error: instruction requires the following: 'Ssip'
+
+#--- no-smip.s
+mipopret
+# NO-SMIP: :[[#@LINE-1]]:1: error: instruction requires the following: 'Smip'
+
+#--- invalid-operands.s
+mipopret zero
+# INVALID-OPERANDS: :[[#@LINE-1]]:10: error: unexpected extra operand for instruction
+sipopret zero
+# INVALID-OPERANDS: :[[#@LINE-1]]:10: error: unexpected extra operand for instruction
diff --git a/llvm/test/MC/RISCV/smip-valid.s b/llvm/test/MC/RISCV/smip-valid.s
new file mode 100644
index 0000000000000..6a50ecc2f4e38
--- /dev/null
+++ b/llvm/test/MC/RISCV/smip-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-smip \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck --check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 \
+# RUN: -mattr=+experimental-smip < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-smip -M no-aliases - \
+# RUN: | FileCheck --check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-smip \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck --check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 \
+# RUN: -mattr=+experimental-smip < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-smip -M no-aliases - \
+# RUN: | FileCheck --check-prefix=CHECK-INST %s
+
+# CHECK-INST: mipopret
+# CHECK-ENC: encoding: [0x73,0x00,0x80,0x30]
+mipopret
diff --git a/llvm/test/MC/RISCV/ssip-valid.s b/llvm/test/MC/RISCV/ssip-valid.s
new file mode 100644
index 0000000000000..38a99f2312e0c
--- /dev/null
+++ b/llvm/test/MC/RISCV/ssip-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-ssip \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck --check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 \
+# RUN: -mattr=+experimental-ssip < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-ssip -M no-aliases - \
+# RUN: | FileCheck --check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-ssip \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck --check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 \
+# RUN: -mattr=+experimental-ssip < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-ssip -M no-aliases - \
+# RUN: | FileCheck --check-prefix=CHECK-INST %s
+
+# CHECK-INST: sipopret
+# CHECK-ENC: encoding: [0x73,0x00,0x80,0x10]
+sipopret
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 94261564e8043..0e5fbd7bbfdcd 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1662,11 +1662,15 @@ Experimental extensions
zvzip 0.1
smcsps 0.19
smehv 0.19
+ smeihv 0.19
smijt 0.19
+ smip 0.19
smpmpmt 0.6
sscsps 0.19
ssehv 0.19
+ sseihv 0.19
ssijt 0.19
+ ssip 0.19
svukte 1.0
xqccmt 0.1
xsfmclic 0.1
>From d5729022ee1920917725e0f8f8498c1d050eee52 Mon Sep 17 00:00:00 2001
From: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: Mon, 10 Aug 2026 21:45:41 +0800
Subject: [PATCH 2/3] remove smeihv,sseihv + bump version to 0.20
---
.../Driver/print-supported-extensions-riscv.c | 18 +++--
.../test/Preprocessor/riscv-target-features.c | 72 +++++++------------
llvm/docs/RISCVUsage.rst | 4 +-
llvm/docs/ReleaseNotes.md | 5 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 23 +++---
llvm/test/CodeGen/RISCV/attributes.ll | 40 +++++------
llvm/test/CodeGen/RISCV/features-info.ll | 2 -
llvm/test/MC/RISCV/attribute-arch.s | 38 +++++-----
.../TargetParser/RISCVISAInfoTest.cpp | 18 +++--
9 files changed, 87 insertions(+), 133 deletions(-)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 7ab9adcb4b44a..e4a26948f8eaf 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -270,17 +270,15 @@
// CHECK-NEXT: zvvmtls 0.1 'Zvvmtls' (Matrix Tile Load/Store)
// CHECK-NEXT: zvvmttls 0.1 'Zvvmttls' (Transposing Matrix Tile Load/Store)
// CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data)
-// CHECK-NEXT: smcsps 0.19 'Smcsps' (Conditional Stack Pointer Swap at Machine Level)
-// CHECK-NEXT: smehv 0.19 'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level)
-// CHECK-NEXT: smeihv 0.19 'Smeihv' (External Interrupt Hardware Vectoring at Machine Level)
-// CHECK-NEXT: smijt 0.19 'Smijt' (Interrupt Jump Table at Machine Level)
-// CHECK-NEXT: smip 0.19 'Smip' (Support for Interrupt Handler Push/Pop at Machine Level)
+// CHECK-NEXT: smcsps 0.20 'Smcsps' (Conditional Stack Pointer Swap at Machine Level)
+// CHECK-NEXT: smehv 0.20 'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level)
+// CHECK-NEXT: smijt 0.20 'Smijt' (Interrupt Jump Table at Machine Level)
+// CHECK-NEXT: smip 0.20 'Smip' (Support for Interrupt Handler Push/Pop at Machine Level)
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
-// CHECK-NEXT: sscsps 0.19 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level)
-// CHECK-NEXT: ssehv 0.19 'Ssehv' (Synchronous Exception Hardware Vectoring at Supervisor Level)
-// CHECK-NEXT: sseihv 0.19 'Sseihv' (External Interrupt Hardware Vectoring at Supervisor Level)
-// CHECK-NEXT: ssijt 0.19 'Ssijt' (Interrupt Jump Table at Supervisor Level)
-// CHECK-NEXT: ssip 0.19 'Ssip' (Support for Interrupt Handler Push/Pop at Supervisor Level)
+// CHECK-NEXT: sscsps 0.20 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level)
+// CHECK-NEXT: ssehv 0.20 'Ssehv' (Synchronous Exception Hardware Vectoring at Supervisor Level)
+// CHECK-NEXT: ssijt 0.20 'Ssijt' (Interrupt Jump Table at Supervisor Level)
+// CHECK-NEXT: ssip 0.20 'Ssip' (Support for Interrupt Handler Push/Pop at Supervisor Level)
// CHECK-NEXT: svukte 1.0 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
// CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump)
// CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index e95698c88734f..21147121a8c05 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -39,7 +39,6 @@
// CHECK-NOT: __riscv_smctr{{.*$}}
// CHECK-NOT: __riscv_smdbltrp {{.*$}}
// CHECK-NOT: __riscv_smehv {{.*$}}
-// CHECK-NOT: __riscv_smeihv {{.*$}}
// CHECK-NOT: __riscv_smepmp {{.*$}}
// CHECK-NOT: __riscv_smijt {{.*$}}
// CHECK-NOT: __riscv_smip {{.*$}}
@@ -58,7 +57,6 @@
// CHECK-NOT: __riscv_ssctr{{.*$}}
// CHECK-NOT: __riscv_ssdbltrp {{.*$}}
// CHECK-NOT: __riscv_ssehv {{.*$}}
-// CHECK-NOT: __riscv_sseihv {{.*$}}
// CHECK-NOT: __riscv_ssijt {{.*$}}
// CHECK-NOT: __riscv_ssip {{.*$}}
// CHECK-NOT: __riscv_ssnpm{{.*$}}
@@ -1343,21 +1341,21 @@
// CHECK-SMCNTRPMF-EXT: __riscv_smcntrpmf 1000000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_smcsps0p19 -E -dM %s \
+// RUN: -march=rv32i_smcsps0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCSPS-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_smcsps0p19 -E -dM %s \
+// RUN: -march=rv64i_smcsps0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCSPS-EXT %s
-// CHECK-SMCSPS-EXT: __riscv_smcsps 19000{{$}}
+// CHECK-SMCSPS-EXT: __riscv_smcsps 20000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_sscsps0p19 -E -dM %s \
+// RUN: -march=rv32i_sscsps0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSCSPS-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_sscsps0p19 -E -dM %s \
+// RUN: -march=rv64i_sscsps0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSCSPS-EXT %s
-// CHECK-SSCSPS-EXT: __riscv_smcsps 19000{{$}}
-// CHECK-SSCSPS-EXT: __riscv_sscsps 19000{{$}}
+// CHECK-SSCSPS-EXT: __riscv_smcsps 20000{{$}}
+// CHECK-SSCSPS-EXT: __riscv_sscsps 20000{{$}}
// RUN: %clang --target=riscv32 \
// RUN: -march=rv32ismcsrind1p0 -E -dM %s \
@@ -1416,70 +1414,54 @@
// CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_smijt0p19 -E -dM %s \
+// RUN: -march=rv32i_smijt0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMIJT-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_smijt0p19 -E -dM %s \
+// RUN: -march=rv64i_smijt0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMIJT-EXT %s
-// CHECK-SMIJT-EXT: __riscv_smijt 19000{{$}}
+// CHECK-SMIJT-EXT: __riscv_smijt 20000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_ssijt0p19 -E -dM %s \
+// RUN: -march=rv32i_ssijt0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSIJT-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_ssijt0p19 -E -dM %s \
+// RUN: -march=rv64i_ssijt0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSIJT-EXT %s
-// CHECK-SSIJT-EXT: __riscv_ssijt 19000{{$}}
+// CHECK-SSIJT-EXT: __riscv_ssijt 20000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_smehv0p19 -E -dM %s \
+// RUN: -march=rv32i_smehv0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMEHV-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_smehv0p19 -E -dM %s \
+// RUN: -march=rv64i_smehv0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMEHV-EXT %s
-// CHECK-SMEHV-EXT: __riscv_smehv 19000{{$}}
-// CHECK-SMEHV-EXT: __riscv_smijt 19000{{$}}
+// CHECK-SMEHV-EXT: __riscv_smehv 20000{{$}}
+// CHECK-SMEHV-EXT: __riscv_smijt 20000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_ssehv0p19 -E -dM %s \
+// RUN: -march=rv32i_ssehv0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSEHV-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_ssehv0p19 -E -dM %s \
+// RUN: -march=rv64i_ssehv0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSEHV-EXT %s
-// CHECK-SSEHV-EXT: __riscv_ssehv 19000{{$}}
-// CHECK-SSEHV-EXT: __riscv_ssijt 19000{{$}}
+// CHECK-SSEHV-EXT: __riscv_ssehv 20000{{$}}
+// CHECK-SSEHV-EXT: __riscv_ssijt 20000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_smeihv0p19 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-SMEIHV-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_smeihv0p19 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-SMEIHV-EXT %s
-// CHECK-SMEIHV-EXT: __riscv_smeihv 19000{{$}}
-
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_sseihv0p19 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-SSEIHV-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_sseihv0p19 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-SSEIHV-EXT %s
-// CHECK-SSEIHV-EXT: __riscv_sseihv 19000{{$}}
-
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_smip0p19 -E -dM %s \
+// RUN: -march=rv32i_smip0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMIP-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_smip0p19 -E -dM %s \
+// RUN: -march=rv64i_smip0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMIP-EXT %s
-// CHECK-SMIP-EXT: __riscv_smip 19000{{$}}
+// CHECK-SMIP-EXT: __riscv_smip 20000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_ssip0p19 -E -dM %s \
+// RUN: -march=rv32i_ssip0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSIP-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_ssip0p19 -E -dM %s \
+// RUN: -march=rv64i_ssip0p20 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSIP-EXT %s
-// CHECK-SSIP-EXT: __riscv_ssip 19000{{$}}
+// CHECK-SSIP-EXT: __riscv_ssip 20000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32ismpmpmt0p6 -x c -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 484cc1ef5a7aa..f0639860fb1d5 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -347,8 +347,8 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zicfilp``, ``experimental-zicfiss``
LLVM implements the `1.0 release specification <https://github.com/riscv/riscv-cfi/releases/tag/v1.0>`__.
-``experimental-smcsps``, ``experimental-sscsps``, ``experimental-smijt``, ``experimental-ssijt``, ``experimental-smehv``, ``experimental-ssehv``, ``experimental-smeihv``, ``experimental-sseihv``, ``experimental-smip``, ``experimental-ssip``
- LLVM implements the `0.19 release specification <https://github.com/riscv/riscv-fast-interrupt/releases/tag/v0.19>`__.
+``experimental-smcsps``, ``experimental-sscsps``, ``experimental-smijt``, ``experimental-ssijt``, ``experimental-smehv``, ``experimental-ssehv``, ``experimental-smip``, ``experimental-ssip``
+ LLVM implements the `0.20 release specification <https://github.com/riscv/riscv-fast-interrupt/releases/tag/v0.20>`__.
``experimental-zvbc32e``, ``experimental-zvkgs``
LLVM implements the `0.7 release specification <https://github.com/user-attachments/files/16450464/riscv-crypto-spec-vector-extra_v0.0.7.pdf>`__.
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index e4d72d2234cbd..94f3409534bfd 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -102,9 +102,8 @@ Makes programs 10x faster by doing Special New Thing.
table extensions and the `Smehv` and `Ssehv` synchronous exception hardware
vectoring extensions.
-* Added experimental MC support for the `Smeihv` and `Sseihv` external
- interrupt hardware vectoring extensions and the `Smip` and `Ssip` interrupt
- handler push/pop extensions.
+* Added experimental MC support for the `Smip` and `Ssip` interrupt handler
+ push/pop extensions.
* Bump Svukte extension to 1.0.
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 2221f23dda11f..be104d2468fcf 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1073,13 +1073,13 @@ def FeatureStdExtSmcntrpmf
: RISCVExtension<1, 0, "Cycle and Instret Privilege Mode Filtering">;
def FeatureStdExtSmcsps
- : RISCVExperimentalExtension<0, 19,
+ : RISCVExperimentalExtension<0, 20,
"Conditional Stack Pointer Swap at Machine Level">;
def HasStdExtSmcsps : Predicate<"Subtarget->hasStdExtSmcsps()">,
AssemblerPredicate<(all_of FeatureStdExtSmcsps),
"'Smcsps' (Conditional Stack Pointer Swap at Machine Level)">;
def FeatureStdExtSscsps
- : RISCVExperimentalExtension<0, 19,
+ : RISCVExperimentalExtension<0, 20,
"Conditional Stack Pointer Swap at Supervisor Level",
[FeatureStdExtSmcsps]>;
def HasStdExtSscsps : Predicate<"Subtarget->hasStdExtSscsps()">,
@@ -1100,37 +1100,30 @@ def FeatureStdExtSmepmp
: RISCVExtension<1, 0, "Enhanced Physical Memory Protection">;
def FeatureStdExtSmijt
- : RISCVExperimentalExtension<0, 19,
+ : RISCVExperimentalExtension<0, 20,
"Interrupt Jump Table at Machine Level">;
def FeatureStdExtSsijt
- : RISCVExperimentalExtension<0, 19,
+ : RISCVExperimentalExtension<0, 20,
"Interrupt Jump Table at Supervisor Level">;
def FeatureStdExtSmehv
- : RISCVExperimentalExtension<0, 19,
+ : RISCVExperimentalExtension<0, 20,
"Synchronous Exception Hardware Vectoring at Machine Level",
[FeatureStdExtSmijt]>;
def FeatureStdExtSsehv
- : RISCVExperimentalExtension<0, 19,
+ : RISCVExperimentalExtension<0, 20,
"Synchronous Exception Hardware Vectoring at Supervisor Level",
[FeatureStdExtSsijt]>;
-def FeatureStdExtSmeihv
- : RISCVExperimentalExtension<0, 19,
- "External Interrupt Hardware Vectoring at Machine Level">;
-def FeatureStdExtSseihv
- : RISCVExperimentalExtension<0, 19,
- "External Interrupt Hardware Vectoring at Supervisor Level">;
-
def FeatureStdExtSmip
- : RISCVExperimentalExtension<0, 19,
+ : RISCVExperimentalExtension<0, 20,
"Support for Interrupt Handler Push/Pop at Machine Level">;
def HasStdExtSmip : Predicate<"Subtarget->hasStdExtSmip()">,
AssemblerPredicate<(all_of FeatureStdExtSmip),
"'Smip' (Support for Interrupt Handler Push/Pop at "
"Machine Level)">;
def FeatureStdExtSsip
- : RISCVExperimentalExtension<0, 19,
+ : RISCVExperimentalExtension<0, 20,
"Support for Interrupt Handler Push/Pop at Supervisor Level">;
def HasStdExtSsip : Predicate<"Subtarget->hasStdExtSsip()">,
AssemblerPredicate<(all_of FeatureStdExtSsip),
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 363b78e1e46b8..0d304edb9aacb 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -135,8 +135,6 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssijt %s -o - | FileCheck --check-prefix=RV32SSIJT %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smehv %s -o - | FileCheck --check-prefix=RV32SMEHV %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssehv %s -o - | FileCheck --check-prefix=RV32SSEHV %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-smeihv %s -o - | FileCheck --check-prefix=RV32SMEIHV %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-sseihv %s -o - | FileCheck --check-prefix=RV32SSEIHV %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smip %s -o - | FileCheck --check-prefix=RV32SMIP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssip %s -o - | FileCheck --check-prefix=RV32SSIP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SMPMPMT %s
@@ -312,8 +310,6 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssijt %s -o - | FileCheck --check-prefix=RV64SSIJT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smehv %s -o - | FileCheck --check-prefix=RV64SMEHV %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssehv %s -o - | FileCheck --check-prefix=RV64SSEHV %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-smeihv %s -o - | FileCheck --check-prefix=RV64SMEIHV %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-sseihv %s -o - | FileCheck --check-prefix=RV64SSEIHV %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smip %s -o - | FileCheck --check-prefix=RV64SMIP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssip %s -o - | FileCheck --check-prefix=RV64SSIP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smpmpmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SMPMPMT %s
@@ -492,17 +488,15 @@
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
; RV32SMCNTRPMF: .attribute 5, "rv32i2p1_smcntrpmf1p0"
-; RV32SMCSPS: .attribute 5, "rv32i2p1_smcsps0p19"
-; RV32SSCSPS: .attribute 5, "rv32i2p1_smcsps0p19_sscsps0p19"
+; RV32SMCSPS: .attribute 5, "rv32i2p1_smcsps0p20"
+; RV32SSCSPS: .attribute 5, "rv32i2p1_smcsps0p20_sscsps0p20"
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
-; RV32SMIJT: .attribute 5, "rv32i2p1_smijt0p19"
-; RV32SSIJT: .attribute 5, "rv32i2p1_ssijt0p19"
-; RV32SMEHV: .attribute 5, "rv32i2p1_smehv0p19_smijt0p19"
-; RV32SSEHV: .attribute 5, "rv32i2p1_ssehv0p19_ssijt0p19"
-; RV32SMEIHV: .attribute 5, "rv32i2p1_smeihv0p19"
-; RV32SSEIHV: .attribute 5, "rv32i2p1_sseihv0p19"
-; RV32SMIP: .attribute 5, "rv32i2p1_smip0p19"
-; RV32SSIP: .attribute 5, "rv32i2p1_ssip0p19"
+; RV32SMIJT: .attribute 5, "rv32i2p1_smijt0p20"
+; RV32SSIJT: .attribute 5, "rv32i2p1_ssijt0p20"
+; RV32SMEHV: .attribute 5, "rv32i2p1_smehv0p20_smijt0p20"
+; RV32SSEHV: .attribute 5, "rv32i2p1_ssehv0p20_ssijt0p20"
+; RV32SMIP: .attribute 5, "rv32i2p1_smip0p20"
+; RV32SSIP: .attribute 5, "rv32i2p1_ssip0p20"
; RV32SMPMPMT: .attribute 5, "rv32i2p1_smpmpmt0p6"
; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
@@ -666,17 +660,15 @@
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
; RV64SMCNTRPMF: .attribute 5, "rv64i2p1_smcntrpmf1p0"
-; RV64SMCSPS: .attribute 5, "rv64i2p1_smcsps0p19"
-; RV64SSCSPS: .attribute 5, "rv64i2p1_smcsps0p19_sscsps0p19"
+; RV64SMCSPS: .attribute 5, "rv64i2p1_smcsps0p20"
+; RV64SSCSPS: .attribute 5, "rv64i2p1_smcsps0p20_sscsps0p20"
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
-; RV64SMIJT: .attribute 5, "rv64i2p1_smijt0p19"
-; RV64SSIJT: .attribute 5, "rv64i2p1_ssijt0p19"
-; RV64SMEHV: .attribute 5, "rv64i2p1_smehv0p19_smijt0p19"
-; RV64SSEHV: .attribute 5, "rv64i2p1_ssehv0p19_ssijt0p19"
-; RV64SMEIHV: .attribute 5, "rv64i2p1_smeihv0p19"
-; RV64SSEIHV: .attribute 5, "rv64i2p1_sseihv0p19"
-; RV64SMIP: .attribute 5, "rv64i2p1_smip0p19"
-; RV64SSIP: .attribute 5, "rv64i2p1_ssip0p19"
+; RV64SMIJT: .attribute 5, "rv64i2p1_smijt0p20"
+; RV64SSIJT: .attribute 5, "rv64i2p1_ssijt0p20"
+; RV64SMEHV: .attribute 5, "rv64i2p1_smehv0p20_smijt0p20"
+; RV64SSEHV: .attribute 5, "rv64i2p1_ssehv0p20_ssijt0p20"
+; RV64SMIP: .attribute 5, "rv64i2p1_smip0p20"
+; RV64SSIP: .attribute 5, "rv64i2p1_ssip0p20"
; RV64SMPMPMT: .attribute 5, "rv64i2p1_smpmpmt0p6"
; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index c08d5db853853..e53641c56841a 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -26,13 +26,11 @@
; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
; CHECK-NEXT: experimental-smcsps - 'Smcsps' (Conditional Stack Pointer Swap at Machine Level).
; CHECK-NEXT: experimental-smehv - 'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level).
-; CHECK-NEXT: experimental-smeihv - 'Smeihv' (External Interrupt Hardware Vectoring at Machine Level).
; CHECK-NEXT: experimental-smijt - 'Smijt' (Interrupt Jump Table at Machine Level).
; CHECK-NEXT: experimental-smip - 'Smip' (Support for Interrupt Handler Push/Pop at Machine Level).
; CHECK-NEXT: experimental-smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension).
; CHECK-NEXT: experimental-sscsps - 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level).
; CHECK-NEXT: experimental-ssehv - 'Ssehv' (Synchronous Exception Hardware Vectoring at Supervisor Level).
-; CHECK-NEXT: experimental-sseihv - 'Sseihv' (External Interrupt Hardware Vectoring at Supervisor Level).
; CHECK-NEXT: experimental-ssijt - 'Ssijt' (Interrupt Jump Table at Supervisor Level).
; CHECK-NEXT: experimental-ssip - 'Ssip' (Support for Interrupt Handler Push/Pop at Supervisor Level).
; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 5d39ee3c8ccd4..f802e91b312b4 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -354,38 +354,32 @@
.attribute arch, "rv32i_smcntrpmf1p0"
# CHECK: attribute 5, "rv32i2p1_smcntrpmf1p0"
-.attribute arch, "rv32i_smcsps0p19"
-# CHECK: attribute 5, "rv32i2p1_smcsps0p19"
+.attribute arch, "rv32i_smcsps0p20"
+# CHECK: attribute 5, "rv32i2p1_smcsps0p20"
-.attribute arch, "rv32i_sscsps0p19"
-# CHECK: attribute 5, "rv32i2p1_smcsps0p19_sscsps0p19"
+.attribute arch, "rv32i_sscsps0p20"
+# CHECK: attribute 5, "rv32i2p1_smcsps0p20_sscsps0p20"
.attribute arch, "rv32i_smepmp1p0"
# CHECK: attribute 5, "rv32i2p1_smepmp1p0"
-.attribute arch, "rv32i_smijt0p19"
-# CHECK: attribute 5, "rv32i2p1_smijt0p19"
+.attribute arch, "rv32i_smijt0p20"
+# CHECK: attribute 5, "rv32i2p1_smijt0p20"
-.attribute arch, "rv32i_ssijt0p19"
-# CHECK: attribute 5, "rv32i2p1_ssijt0p19"
+.attribute arch, "rv32i_ssijt0p20"
+# CHECK: attribute 5, "rv32i2p1_ssijt0p20"
-.attribute arch, "rv32i_smehv0p19"
-# CHECK: attribute 5, "rv32i2p1_smehv0p19_smijt0p19"
+.attribute arch, "rv32i_smehv0p20"
+# CHECK: attribute 5, "rv32i2p1_smehv0p20_smijt0p20"
-.attribute arch, "rv32i_ssehv0p19"
-# CHECK: attribute 5, "rv32i2p1_ssehv0p19_ssijt0p19"
+.attribute arch, "rv32i_ssehv0p20"
+# CHECK: attribute 5, "rv32i2p1_ssehv0p20_ssijt0p20"
-.attribute arch, "rv32i_smeihv0p19"
-# CHECK: attribute 5, "rv32i2p1_smeihv0p19"
+.attribute arch, "rv32i_smip0p20"
+# CHECK: attribute 5, "rv32i2p1_smip0p20"
-.attribute arch, "rv32i_sseihv0p19"
-# CHECK: attribute 5, "rv32i2p1_sseihv0p19"
-
-.attribute arch, "rv32i_smip0p19"
-# CHECK: attribute 5, "rv32i2p1_smip0p19"
-
-.attribute arch, "rv32i_ssip0p19"
-# CHECK: attribute 5, "rv32i2p1_ssip0p19"
+.attribute arch, "rv32i_ssip0p20"
+# CHECK: attribute 5, "rv32i2p1_ssip0p20"
.attribute arch, "rv32i_smpmpmt0p6"
# CHECK: attribute 5, "rv32i2p1_smpmpmt0p6"
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 0e5fbd7bbfdcd..e0d7b053731ad 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1660,17 +1660,15 @@ Experimental extensions
zvvmtls 0.1
zvvmttls 0.1
zvzip 0.1
- smcsps 0.19
- smehv 0.19
- smeihv 0.19
- smijt 0.19
- smip 0.19
+ smcsps 0.20
+ smehv 0.20
+ smijt 0.20
+ smip 0.20
smpmpmt 0.6
- sscsps 0.19
- ssehv 0.19
- sseihv 0.19
- ssijt 0.19
- ssip 0.19
+ sscsps 0.20
+ ssehv 0.20
+ ssijt 0.20
+ ssip 0.20
svukte 1.0
xqccmt 0.1
xsfmclic 0.1
>From f88b4a44a8538315d68d7a5706e4cfcfad017a80 Mon Sep 17 00:00:00 2001
From: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: Tue, 11 Aug 2026 17:58:54 +0800
Subject: [PATCH 3/3] remove some attributes for now.
---
llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td | 3 ---
1 file changed, 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td b/llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td
index 29baca4848a53..19d27003042be 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td
@@ -6,8 +6,6 @@
//
//===----------------------------------------------------------------------===//
-let mayLoad = 1, Uses = [X2], Defs = [X2, X10, X11, X12, X13, X14, X15],
- isBarrier = 1, isReturn = 1, isTerminator = 1 in {
let Predicates = [HasStdExtSmip] in
def MIPOPRET : Priv<"mipopret", 0b0011000>, Sched<[]> {
let rd = 0;
@@ -21,4 +19,3 @@ def SIPOPRET : Priv<"sipopret", 0b0001000>, Sched<[]> {
let rs1 = 0;
let rs2 = 0b01000;
}
-} // isBarrier = 1, isReturn = 1, isTerminator = 1
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