[clang] [llvm] [RISCV][MC] Add experimental Smip, and Ssip support (PR #215095)

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zhangweize9-cyber wrote:

> I think maybe the way forward is to add only the assembly info, and leave out the codegen info (i.e. `mayLoad`, `Uses`, `Defs`, `isBarrier`, `isReturn`, `isTerminator`), which we can come back to when we implement code generation for these instructions.

By the way, in which future major version are these features expected to be improved and supported?



https://github.com/llvm/llvm-project/pull/215095