[clang] [CIR][RISCV] Support vector buitlins codegen (PR #199889)

[Pengcheng Wang via cfe-commits]

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+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
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wangpc-pp wrote:

What is your plan for others?  And I don't like duplicating all these RVV tests, the amount is huge.

https://github.com/llvm/llvm-project/pull/199889