[clang] [CIR][RISCV] Support vector buitlins codegen (PR #199889)
Jianjian Guan via cfe-commits
cfe-commits at lists.llvm.org
Thu Jun 4 23:58:13 PDT 2026
https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/199889
>From d961282991ef646c39f0656779185ef43876f68b Mon Sep 17 00:00:00 2001
From: Jianjian GUAN <jacquesguan at me.com>
Date: Mon, 25 May 2026 17:08:10 +0800
Subject: [PATCH 1/2] [CIR][RISCV] Support vector buitlins codegen
---
clang/include/clang/Basic/CMakeLists.txt | 3 +
clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp | 42 +-
clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 45 +
.../rvv/non-policy/non-overloaded/vadd.c | 2299 +++++++++++++++++
clang/utils/TableGen/RISCVVEmitter.cpp | 112 +
clang/utils/TableGen/TableGen.cpp | 7 +
clang/utils/TableGen/TableGenBackends.h | 2 +
7 files changed, 2504 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CIR/CodeGenBuiltins/RISCV/rvv/non-policy/non-overloaded/vadd.c
diff --git a/clang/include/clang/Basic/CMakeLists.txt b/clang/include/clang/Basic/CMakeLists.txt
index 20172622ca424..b7e8b0d185667 100644
--- a/clang/include/clang/Basic/CMakeLists.txt
+++ b/clang/include/clang/Basic/CMakeLists.txt
@@ -226,6 +226,9 @@ clang_tablegen(riscv_vector_builtins.inc -gen-riscv-vector-builtins
clang_tablegen(riscv_vector_builtin_cg.inc -gen-riscv-vector-builtin-codegen
SOURCE riscv_vector.td
TARGET ClangRISCVVectorBuiltinCG)
+clang_tablegen(riscv_vector_builtin_cir_cg.inc -gen-riscv-vector-builtin-cir-codegen
+ SOURCE riscv_vector.td
+ TARGET ClangRISCVVectorBuiltinCIRCG)
clang_tablegen(riscv_vector_builtin_sema.inc -gen-riscv-vector-builtin-sema
SOURCE riscv_vector.td
TARGET ClangRISCVVectorBuiltinSema)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
index ec262922be942..10119a5a6dcbc 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
@@ -30,6 +30,7 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
StringRef intrinsicName;
mlir::Type returnType = convertType(e->getType());
+ mlir::Location loc = getLoc(e->getSourceRange());
llvm::SmallVector<mlir::Value> ops;
// `iceArguments` is a bitmap indicating whether the argument at the i-th bit
@@ -37,9 +38,33 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
unsigned iceArguments = 0;
ASTContext::GetBuiltinTypeError error;
getContext().GetBuiltinType(builtinID, error, &iceArguments);
- assert(error == ASTContext::GE_None && "Should not codegen an error");
- for (auto [idx, arg] : llvm::enumerate(e->arguments()))
+
+ // RVV vector builtins use a special type overload mechanism (no type string).
+ if (error == ASTContext::GE_Missing_type) {
+ // Vector intrinsics don't have a type string.
+ assert(builtinID >= clang::RISCV::FirstRVVBuiltin &&
+ builtinID <= clang::RISCV::LastRVVBuiltin);
+ iceArguments = 0;
+ if (builtinID == RISCVVector::BI__builtin_rvv_vget_v ||
+ builtinID == RISCVVector::BI__builtin_rvv_vset_v)
+ iceArguments = 1 << 1;
+ } else {
+ assert(error == ASTContext::GE_None && "Unexpected error");
+ }
+
+ for (auto [idx, arg] : llvm::enumerate(e->arguments())) {
+ // Handle aggregate argument, namely RVV tuple types in segment load/store
+ if (hasAggregateEvaluationKind(arg->getType())) {
+ LValue lv = emitAggExprToLValue(arg);
+ ops.push_back(builder.createLoad(loc, lv.getAddress()));
+ continue;
+ }
ops.push_back(emitScalarOrConstFoldImmArg(iceArguments, idx, arg));
+ }
+
+ // TODO: Handle ManualCodegen.
+ bool hasCirManualCodegen = false;
+ int PolicyAttrs = 0;
switch (builtinID) {
default:
@@ -132,7 +157,6 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
// Zbb
case RISCV::BI__builtin_riscv_clz_32:
case RISCV::BI__builtin_riscv_clz_64: {
- mlir::Location loc = getLoc(e->getSourceRange());
auto op = cir::BitClzOp::create(builder, loc, ops[0],
/*poison_zero=*/false);
mlir::Value result = op.getResult();
@@ -142,7 +166,6 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
}
case RISCV::BI__builtin_riscv_ctz_32:
case RISCV::BI__builtin_riscv_ctz_64: {
- mlir::Location loc = getLoc(e->getSourceRange());
auto op = cir::BitCtzOp::create(builder, loc, ops[0],
/*poison_zero=*/false);
mlir::Value result = op.getResult();
@@ -202,9 +225,16 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
return mlir::Value{};
}
- // TODO: Handle vector builtins in tablegen.
+#include "clang/Basic/riscv_vector_builtin_cir_cg.inc"
+ // TODO: Handle Andes and SiFive vecotor builtin.
+ }
+
+ if (hasCirManualCodegen) {
+ cgm.errorNYI(e->getSourceRange(),
+ std::string("unimplemented RISC-V vector builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
}
- mlir::Location loc = getLoc(e->getSourceRange());
return builder.emitIntrinsicCallOp(loc, intrinsicName, returnType, ops);
}
diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
index 85b7e854abb7f..1a39bb86d874f 100644
--- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
@@ -405,6 +405,51 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
/*is_scalable=*/true);
break;
+// RISC-V vector types.
+#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF, \
+ IsSigned) \
+ case BuiltinType::Id: { \
+ auto eltTy = \
+ IsSigned ? builder.getSIntNTy(ElBits) : builder.getUIntNTy(ElBits); \
+ resultType = cir::VectorType::get(eltTy, NumEls, /*is_scalable=*/true); \
+ break; \
+ }
+#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \
+ case BuiltinType::Id: { \
+ mlir::Type eltTy; \
+ if (ElBits == 16) \
+ eltTy = builder.getFp16Ty(); \
+ else if (ElBits == 32) \
+ eltTy = builder.getSingleTy(); \
+ else if (ElBits == 64) \
+ eltTy = builder.getDoubleTy(); \
+ else \
+ llvm_unreachable("unsupported RVV FP element width"); \
+ resultType = cir::VectorType::get(eltTy, NumEls, /*is_scalable=*/true); \
+ break; \
+ }
+#define RVV_VECTOR_TYPE_BFLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \
+ case BuiltinType::Id: { \
+ resultType = cir::VectorType::get(builder.getBfloat6Ty(), NumEls, \
+ /*is_scalable=*/true); \
+ break; \
+ }
+#define RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls) \
+ case BuiltinType::Id: { \
+ resultType = cir::VectorType::get(builder.getUIntNTy(1), NumEls, \
+ /*is_scalable=*/true); \
+ break; \
+ }
+// RVV_VECTOR_TYPE_OFP8 maps to RVV_VECTOR_TYPE_INT (unsigned)
+#define RVV_VECTOR_TYPE_OFP8(Name, Id, SingletonId, NumEls, E5m2) \
+ case BuiltinType::Id: { \
+ resultType = cir::VectorType::get(builder.getUIntNTy(8), NumEls, \
+ /*is_scalable=*/true); \
+ break; \
+ }
+
+#include "clang/Basic/RISCVVTypes.def"
+
// Unsigned integral types.
case BuiltinType::Char8:
case BuiltinType::Char16:
diff --git a/clang/test/CIR/CodeGenBuiltins/RISCV/rvv/non-policy/non-overloaded/vadd.c b/clang/test/CIR/CodeGenBuiltins/RISCV/rvv/non-policy/non-overloaded/vadd.c
new file mode 100644
index 0000000000000..9a7f2938fbbe1
--- /dev/null
+++ b/clang/test/CIR/CodeGenBuiltins/RISCV/rvv/non-policy/non-overloaded/vadd.c
@@ -0,0 +1,2299 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -fclangir -emit-cir %s -o - | FileCheck %s --check-prefix=CIR
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -fclangir -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s --check-prefix=CHECK-RV64
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_vector.h>
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8mf8(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s8i>, !cir.vector<[1] x !s8i>, !cir.vector<[1] x !s8i>, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8
+// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8mf8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8mf8(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s8i>, !cir.vector<[1] x !s8i>, !s8i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8
+// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8(vint8mf8_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8mf8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8mf4(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s8i>, !cir.vector<[2] x !s8i>, !cir.vector<[2] x !s8i>, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4
+// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
+//
+vint8mf4_t test_vadd_vv_i8mf4(vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8mf4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8mf4(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s8i>, !cir.vector<[2] x !s8i>, !s8i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4
+// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
+//
+vint8mf4_t test_vadd_vx_i8mf4(vint8mf4_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8mf4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8mf2(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s8i>, !cir.vector<[4] x !s8i>, !cir.vector<[4] x !s8i>, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
+//
+vint8mf2_t test_vadd_vv_i8mf2(vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8mf2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8mf2(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s8i>, !cir.vector<[4] x !s8i>, !s8i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
+//
+vint8mf2_t test_vadd_vx_i8mf2(vint8mf2_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8mf2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8m1(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s8i>, !cir.vector<[8] x !s8i>, !cir.vector<[8] x !s8i>, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vadd_vv_i8m1(vint8m1_t op1, vint8m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8m1(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s8i>, !cir.vector<[8] x !s8i>, !s8i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vadd_vx_i8m1(vint8m1_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8m2(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !s8i>, !cir.vector<[16] x !s8i>, !cir.vector<[16] x !s8i>, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vint8m2_t test_vadd_vv_i8m2(vint8m2_t op1, vint8m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8m2(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !s8i>, !cir.vector<[16] x !s8i>, !s8i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vadd_vx_i8m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vint8m2_t test_vadd_vx_i8m2(vint8m2_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8m4(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !s8i>, !cir.vector<[32] x !s8i>, !cir.vector<[32] x !s8i>, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vadd_vv_i8m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vint8m4_t test_vadd_vv_i8m4(vint8m4_t op1, vint8m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8m4(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !s8i>, !cir.vector<[32] x !s8i>, !s8i, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vadd_vx_i8m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vint8m4_t test_vadd_vx_i8m4(vint8m4_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8m8(
+// CIR-SAME: -> !cir.vector<[64]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[64] x !s8i>, !cir.vector<[64] x !s8i>, !cir.vector<[64] x !s8i>, !u64i) -> !cir.vector<[64]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vadd_vv_i8m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vint8m8_t test_vadd_vv_i8m8(vint8m8_t op1, vint8m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8m8(
+// CIR-SAME: -> !cir.vector<[64]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[64] x !s8i>, !cir.vector<[64] x !s8i>, !s8i, !u64i) -> !cir.vector<[64]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vadd_vx_i8m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vint8m8_t test_vadd_vx_i8m8(vint8m8_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i16mf4(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s16i>, !cir.vector<[1] x !s16i>, !cir.vector<[1] x !s16i>, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vadd_vv_i16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
+//
+vint16mf4_t test_vadd_vv_i16mf4(vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
+ return __riscv_vadd_vv_i16mf4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i16mf4(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s16i>, !cir.vector<[1] x !s16i>, !s16i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vadd_vx_i16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i16 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
+//
+vint16mf4_t test_vadd_vx_i16mf4(vint16mf4_t op1, int16_t op2, size_t vl) {
+ return __riscv_vadd_vx_i16mf4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i16mf2(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s16i>, !cir.vector<[2] x !s16i>, !cir.vector<[2] x !s16i>, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vadd_vv_i16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
+//
+vint16mf2_t test_vadd_vv_i16mf2(vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i16mf2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i16mf2(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s16i>, !cir.vector<[2] x !s16i>, !s16i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vadd_vx_i16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i16 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
+//
+vint16mf2_t test_vadd_vx_i16mf2(vint16mf2_t op1, int16_t op2, size_t vl) {
+ return __riscv_vadd_vx_i16mf2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i16m1(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s16i>, !cir.vector<[4] x !s16i>, !cir.vector<[4] x !s16i>, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vadd_vv_i16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vadd_vv_i16m1(vint16m1_t op1, vint16m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_i16m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i16m1(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s16i>, !cir.vector<[4] x !s16i>, !s16i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vadd_vx_i16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i16 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vadd_vx_i16m1(vint16m1_t op1, int16_t op2, size_t vl) {
+ return __riscv_vadd_vx_i16m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i16m2(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s16i>, !cir.vector<[8] x !s16i>, !cir.vector<[8] x !s16i>, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vadd_vv_i16m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vint16m2_t test_vadd_vv_i16m2(vint16m2_t op1, vint16m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i16m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i16m2(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s16i>, !cir.vector<[8] x !s16i>, !s16i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vadd_vx_i16m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i16 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vint16m2_t test_vadd_vx_i16m2(vint16m2_t op1, int16_t op2, size_t vl) {
+ return __riscv_vadd_vx_i16m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i16m4(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !s16i>, !cir.vector<[16] x !s16i>, !cir.vector<[16] x !s16i>, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vadd_vv_i16m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vint16m4_t test_vadd_vv_i16m4(vint16m4_t op1, vint16m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_i16m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i16m4(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !s16i>, !cir.vector<[16] x !s16i>, !s16i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vadd_vx_i16m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i16 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vint16m4_t test_vadd_vx_i16m4(vint16m4_t op1, int16_t op2, size_t vl) {
+ return __riscv_vadd_vx_i16m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i16m8(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !s16i>, !cir.vector<[32] x !s16i>, !cir.vector<[32] x !s16i>, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vadd_vv_i16m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vint16m8_t test_vadd_vv_i16m8(vint16m8_t op1, vint16m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_i16m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i16m8(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !s16i>, !cir.vector<[32] x !s16i>, !s16i, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vadd_vx_i16m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i16 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vint16m8_t test_vadd_vx_i16m8(vint16m8_t op1, int16_t op2, size_t vl) {
+ return __riscv_vadd_vx_i16m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i32mf2(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s32i>, !cir.vector<[1] x !s32i>, !cir.vector<[1] x !s32i>, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vadd_vv_i32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vadd_vv_i32mf2(vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i32mf2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i32mf2(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s32i>, !cir.vector<[1] x !s32i>, !s32i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vadd_vx_i32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vadd_vx_i32mf2(vint32mf2_t op1, int32_t op2, size_t vl) {
+ return __riscv_vadd_vx_i32mf2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i32m1(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s32i>, !cir.vector<[2] x !s32i>, !cir.vector<[2] x !s32i>, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vadd_vv_i32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vadd_vv_i32m1(vint32m1_t op1, vint32m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_i32m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i32m1(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s32i>, !cir.vector<[2] x !s32i>, !s32i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vadd_vx_i32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vadd_vx_i32m1(vint32m1_t op1, int32_t op2, size_t vl) {
+ return __riscv_vadd_vx_i32m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i32m2(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s32i>, !cir.vector<[4] x !s32i>, !cir.vector<[4] x !s32i>, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vadd_vv_i32m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vadd_vv_i32m2(vint32m2_t op1, vint32m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i32m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i32m2(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s32i>, !cir.vector<[4] x !s32i>, !s32i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vadd_vx_i32m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vadd_vx_i32m2(vint32m2_t op1, int32_t op2, size_t vl) {
+ return __riscv_vadd_vx_i32m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i32m4(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s32i>, !cir.vector<[8] x !s32i>, !cir.vector<[8] x !s32i>, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vadd_vv_i32m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vadd_vv_i32m4(vint32m4_t op1, vint32m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_i32m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i32m4(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s32i>, !cir.vector<[8] x !s32i>, !s32i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vadd_vx_i32m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vadd_vx_i32m4(vint32m4_t op1, int32_t op2, size_t vl) {
+ return __riscv_vadd_vx_i32m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i32m8(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !s32i>, !cir.vector<[16] x !s32i>, !cir.vector<[16] x !s32i>, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vadd_vv_i32m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vadd_vv_i32m8(vint32m8_t op1, vint32m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_i32m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i32m8(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !s32i>, !cir.vector<[16] x !s32i>, !s32i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vadd_vx_i32m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vadd_vx_i32m8(vint32m8_t op1, int32_t op2, size_t vl) {
+ return __riscv_vadd_vx_i32m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i64m1(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s64i>, !cir.vector<[1] x !s64i>, !cir.vector<[1] x !s64i>, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vadd_vv_i64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vadd_vv_i64m1(vint64m1_t op1, vint64m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_i64m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i64m1(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s64i>, !cir.vector<[1] x !s64i>, !s64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vadd_vx_i64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vadd_vx_i64m1(vint64m1_t op1, int64_t op2, size_t vl) {
+ return __riscv_vadd_vx_i64m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i64m2(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s64i>, !cir.vector<[2] x !s64i>, !cir.vector<[2] x !s64i>, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vadd_vv_i64m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vint64m2_t test_vadd_vv_i64m2(vint64m2_t op1, vint64m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i64m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i64m2(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s64i>, !cir.vector<[2] x !s64i>, !s64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vadd_vx_i64m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vint64m2_t test_vadd_vx_i64m2(vint64m2_t op1, int64_t op2, size_t vl) {
+ return __riscv_vadd_vx_i64m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i64m4(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s64i>, !cir.vector<[4] x !s64i>, !cir.vector<[4] x !s64i>, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vadd_vv_i64m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vint64m4_t test_vadd_vv_i64m4(vint64m4_t op1, vint64m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_i64m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i64m4(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s64i>, !cir.vector<[4] x !s64i>, !s64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vadd_vx_i64m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vint64m4_t test_vadd_vx_i64m4(vint64m4_t op1, int64_t op2, size_t vl) {
+ return __riscv_vadd_vx_i64m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i64m8(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s64i>, !cir.vector<[8] x !s64i>, !cir.vector<[8] x !s64i>, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vadd_vv_i64m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vint64m8_t test_vadd_vv_i64m8(vint64m8_t op1, vint64m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_i64m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i64m8(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s64i>, !cir.vector<[8] x !s64i>, !s64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vadd_vx_i64m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vint64m8_t test_vadd_vx_i64m8(vint64m8_t op1, int64_t op2, size_t vl) {
+ return __riscv_vadd_vx_i64m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8mf8(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u8i>, !cir.vector<[1] x !u8i>, !cir.vector<[1] x !u8i>, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vadd_vv_u8mf8
+// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8mf8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8mf8(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u8i>, !cir.vector<[1] x !u8i>, !u8i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vadd_vx_u8mf8
+// CHECK-RV64-SAME: (<vscale x 1 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8(vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8mf8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8mf4(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u8i>, !cir.vector<[2] x !u8i>, !cir.vector<[2] x !u8i>, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vadd_vv_u8mf4
+// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
+//
+vuint8mf4_t test_vadd_vv_u8mf4(vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8mf4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8mf4(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u8i>, !cir.vector<[2] x !u8i>, !u8i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vadd_vx_u8mf4
+// CHECK-RV64-SAME: (<vscale x 2 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
+//
+vuint8mf4_t test_vadd_vx_u8mf4(vuint8mf4_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8mf4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8mf2(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u8i>, !cir.vector<[4] x !u8i>, !cir.vector<[4] x !u8i>, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vadd_vv_u8mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
+//
+vuint8mf2_t test_vadd_vv_u8mf2(vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8mf2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8mf2(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u8i>, !cir.vector<[4] x !u8i>, !u8i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vadd_vx_u8mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
+//
+vuint8mf2_t test_vadd_vx_u8mf2(vuint8mf2_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8mf2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8m1(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u8i>, !cir.vector<[8] x !u8i>, !cir.vector<[8] x !u8i>, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vadd_vv_u8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vadd_vv_u8m1(vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8m1(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u8i>, !cir.vector<[8] x !u8i>, !u8i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vadd_vx_u8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vadd_vx_u8m1(vuint8m1_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8m2(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !u8i>, !cir.vector<[16] x !u8i>, !cir.vector<[16] x !u8i>, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vadd_vv_u8m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vuint8m2_t test_vadd_vv_u8m2(vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8m2(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !u8i>, !cir.vector<[16] x !u8i>, !u8i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vadd_vx_u8m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vuint8m2_t test_vadd_vx_u8m2(vuint8m2_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8m4(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !u8i>, !cir.vector<[32] x !u8i>, !cir.vector<[32] x !u8i>, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vadd_vv_u8m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vuint8m4_t test_vadd_vv_u8m4(vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8m4(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !u8i>, !cir.vector<[32] x !u8i>, !u8i, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vadd_vx_u8m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vuint8m4_t test_vadd_vx_u8m4(vuint8m4_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8m8(
+// CIR-SAME: -> !cir.vector<[64]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[64] x !u8i>, !cir.vector<[64] x !u8i>, !cir.vector<[64] x !u8i>, !u64i) -> !cir.vector<[64]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vadd_vv_u8m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vuint8m8_t test_vadd_vv_u8m8(vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8m8(
+// CIR-SAME: -> !cir.vector<[64]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[64] x !u8i>, !cir.vector<[64] x !u8i>, !u8i, !u64i) -> !cir.vector<[64]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vadd_vx_u8m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], i8 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vuint8m8_t test_vadd_vx_u8m8(vuint8m8_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u16mf4(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u16i>, !cir.vector<[1] x !u16i>, !cir.vector<[1] x !u16i>, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vadd_vv_u16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
+//
+vuint16mf4_t test_vadd_vv_u16mf4(vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
+ return __riscv_vadd_vv_u16mf4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u16mf4(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u16i>, !cir.vector<[1] x !u16i>, !u16i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vadd_vx_u16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[OP1:%.*]], i16 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
+//
+vuint16mf4_t test_vadd_vx_u16mf4(vuint16mf4_t op1, uint16_t op2, size_t vl) {
+ return __riscv_vadd_vx_u16mf4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u16mf2(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u16i>, !cir.vector<[2] x !u16i>, !cir.vector<[2] x !u16i>, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vadd_vv_u16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
+//
+vuint16mf2_t test_vadd_vv_u16mf2(vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u16mf2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u16mf2(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u16i>, !cir.vector<[2] x !u16i>, !u16i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vadd_vx_u16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[OP1:%.*]], i16 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
+//
+vuint16mf2_t test_vadd_vx_u16mf2(vuint16mf2_t op1, uint16_t op2, size_t vl) {
+ return __riscv_vadd_vx_u16mf2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u16m1(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u16i>, !cir.vector<[4] x !u16i>, !cir.vector<[4] x !u16i>, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vadd_vv_u16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vadd_vv_u16m1(vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_u16m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u16m1(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u16i>, !cir.vector<[4] x !u16i>, !u16i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vadd_vx_u16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[OP1:%.*]], i16 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vadd_vx_u16m1(vuint16m1_t op1, uint16_t op2, size_t vl) {
+ return __riscv_vadd_vx_u16m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u16m2(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u16i>, !cir.vector<[8] x !u16i>, !cir.vector<[8] x !u16i>, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vadd_vv_u16m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vuint16m2_t test_vadd_vv_u16m2(vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u16m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u16m2(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u16i>, !cir.vector<[8] x !u16i>, !u16i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vadd_vx_u16m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[OP1:%.*]], i16 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vuint16m2_t test_vadd_vx_u16m2(vuint16m2_t op1, uint16_t op2, size_t vl) {
+ return __riscv_vadd_vx_u16m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u16m4(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !u16i>, !cir.vector<[16] x !u16i>, !cir.vector<[16] x !u16i>, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vadd_vv_u16m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vuint16m4_t test_vadd_vv_u16m4(vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_u16m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u16m4(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !u16i>, !cir.vector<[16] x !u16i>, !u16i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vadd_vx_u16m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[OP1:%.*]], i16 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vuint16m4_t test_vadd_vx_u16m4(vuint16m4_t op1, uint16_t op2, size_t vl) {
+ return __riscv_vadd_vx_u16m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u16m8(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !u16i>, !cir.vector<[32] x !u16i>, !cir.vector<[32] x !u16i>, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vadd_vv_u16m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vuint16m8_t test_vadd_vv_u16m8(vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_u16m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u16m8(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !u16i>, !cir.vector<[32] x !u16i>, !u16i, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vadd_vx_u16m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[OP1:%.*]], i16 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], i16 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vuint16m8_t test_vadd_vx_u16m8(vuint16m8_t op1, uint16_t op2, size_t vl) {
+ return __riscv_vadd_vx_u16m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u32mf2(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u32i>, !cir.vector<[1] x !u32i>, !cir.vector<[1] x !u32i>, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vadd_vv_u32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vadd_vv_u32mf2(vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u32mf2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u32mf2(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u32i>, !cir.vector<[1] x !u32i>, !u32i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vadd_vx_u32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vadd_vx_u32mf2(vuint32mf2_t op1, uint32_t op2, size_t vl) {
+ return __riscv_vadd_vx_u32mf2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u32m1(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u32i>, !cir.vector<[2] x !u32i>, !cir.vector<[2] x !u32i>, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vadd_vv_u32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vadd_vv_u32m1(vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_u32m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u32m1(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u32i>, !cir.vector<[2] x !u32i>, !u32i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vadd_vx_u32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vadd_vx_u32m1(vuint32m1_t op1, uint32_t op2, size_t vl) {
+ return __riscv_vadd_vx_u32m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u32m2(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u32i>, !cir.vector<[4] x !u32i>, !cir.vector<[4] x !u32i>, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vadd_vv_u32m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_vadd_vv_u32m2(vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u32m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u32m2(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u32i>, !cir.vector<[4] x !u32i>, !u32i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vadd_vx_u32m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_vadd_vx_u32m2(vuint32m2_t op1, uint32_t op2, size_t vl) {
+ return __riscv_vadd_vx_u32m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u32m4(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u32i>, !cir.vector<[8] x !u32i>, !cir.vector<[8] x !u32i>, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vadd_vv_u32m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_vadd_vv_u32m4(vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_u32m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u32m4(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u32i>, !cir.vector<[8] x !u32i>, !u32i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vadd_vx_u32m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_vadd_vx_u32m4(vuint32m4_t op1, uint32_t op2, size_t vl) {
+ return __riscv_vadd_vx_u32m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u32m8(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !u32i>, !cir.vector<[16] x !u32i>, !cir.vector<[16] x !u32i>, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vadd_vv_u32m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vuint32m8_t test_vadd_vv_u32m8(vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_u32m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u32m8(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !u32i>, !cir.vector<[16] x !u32i>, !u32i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vadd_vx_u32m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], i32 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vuint32m8_t test_vadd_vx_u32m8(vuint32m8_t op1, uint32_t op2, size_t vl) {
+ return __riscv_vadd_vx_u32m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u64m1(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u64i>, !cir.vector<[1] x !u64i>, !cir.vector<[1] x !u64i>, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vadd_vv_u64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vadd_vv_u64m1(vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_u64m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u64m1(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u64i>, !cir.vector<[1] x !u64i>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vadd_vx_u64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vadd_vx_u64m1(vuint64m1_t op1, uint64_t op2, size_t vl) {
+ return __riscv_vadd_vx_u64m1(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u64m2(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u64i>, !cir.vector<[2] x !u64i>, !cir.vector<[2] x !u64i>, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vadd_vv_u64m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vuint64m2_t test_vadd_vv_u64m2(vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u64m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u64m2(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u64i>, !cir.vector<[2] x !u64i>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vadd_vx_u64m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vuint64m2_t test_vadd_vx_u64m2(vuint64m2_t op1, uint64_t op2, size_t vl) {
+ return __riscv_vadd_vx_u64m2(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u64m4(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u64i>, !cir.vector<[4] x !u64i>, !cir.vector<[4] x !u64i>, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vadd_vv_u64m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vuint64m4_t test_vadd_vv_u64m4(vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_u64m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u64m4(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u64i>, !cir.vector<[4] x !u64i>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vadd_vx_u64m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vuint64m4_t test_vadd_vx_u64m4(vuint64m4_t op1, uint64_t op2, size_t vl) {
+ return __riscv_vadd_vx_u64m4(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u64m8(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u64i>, !cir.vector<[8] x !u64i>, !cir.vector<[8] x !u64i>, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vadd_vv_u64m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vuint64m8_t test_vadd_vv_u64m8(vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_u64m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u64m8(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u64i>, !cir.vector<[8] x !u64i>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vadd_vx_u64m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], i64 [[OP2]], i64 [[VL]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vuint64m8_t test_vadd_vx_u64m8(vuint64m8_t op1, uint64_t op2, size_t vl) {
+ return __riscv_vadd_vx_u64m8(op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8mf8_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s8i>, !cir.vector<[1] x !s8i>, !cir.vector<[1] x !s8i>, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8_m(vbool64_t mask, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8mf8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8mf8_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s8i>, !cir.vector<[1] x !s8i>, !s8i, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8_m(vbool64_t mask, vint8mf8_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8mf8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8mf4_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s8i>, !cir.vector<[2] x !s8i>, !cir.vector<[2] x !s8i>, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
+//
+vint8mf4_t test_vadd_vv_i8mf4_m(vbool32_t mask, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8mf4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8mf4_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s8i>, !cir.vector<[2] x !s8i>, !s8i, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
+//
+vint8mf4_t test_vadd_vx_i8mf4_m(vbool32_t mask, vint8mf4_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8mf4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8mf2_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s8i>, !cir.vector<[4] x !s8i>, !cir.vector<[4] x !s8i>, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
+//
+vint8mf2_t test_vadd_vv_i8mf2_m(vbool16_t mask, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8mf2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8mf2_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s8i>, !cir.vector<[4] x !s8i>, !s8i, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
+//
+vint8mf2_t test_vadd_vx_i8mf2_m(vbool16_t mask, vint8mf2_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8mf2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8m1_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s8i>, !cir.vector<[8] x !s8i>, !cir.vector<[8] x !s8i>, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vadd_vv_i8m1_m(vbool8_t mask, vint8m1_t op1, vint8m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8m1_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s8i>, !cir.vector<[8] x !s8i>, !s8i, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vadd_vx_i8m1_m(vbool8_t mask, vint8m1_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8m2_m(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !s8i>, !cir.vector<[16] x !s8i>, !cir.vector<[16] x !s8i>, !cir.vector<[16] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vint8m2_t test_vadd_vv_i8m2_m(vbool4_t mask, vint8m2_t op1, vint8m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8m2_m(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !s8i>, !cir.vector<[16] x !s8i>, !s8i, !cir.vector<[16] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vadd_vx_i8m2_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vint8m2_t test_vadd_vx_i8m2_m(vbool4_t mask, vint8m2_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8m4_m(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !s8i>, !cir.vector<[32] x !s8i>, !cir.vector<[32] x !s8i>, !cir.vector<[32] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vadd_vv_i8m4_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vint8m4_t test_vadd_vv_i8m4_m(vbool2_t mask, vint8m4_t op1, vint8m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8m4_m(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !s8i>, !cir.vector<[32] x !s8i>, !s8i, !cir.vector<[32] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vadd_vx_i8m4_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vint8m4_t test_vadd_vx_i8m4_m(vbool2_t mask, vint8m4_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i8m8_m(
+// CIR-SAME: -> !cir.vector<[64]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[64] x !s8i>, !cir.vector<[64] x !s8i>, !cir.vector<[64] x !s8i>, !cir.vector<[64] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[64]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vadd_vv_i8m8_m
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vint8m8_t test_vadd_vv_i8m8_m(vbool1_t mask, vint8m8_t op1, vint8m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_i8m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i8m8_m(
+// CIR-SAME: -> !cir.vector<[64]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[64] x !s8i>, !cir.vector<[64] x !s8i>, !s8i, !cir.vector<[64] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[64]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vadd_vx_i8m8_m
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], i8 [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vint8m8_t test_vadd_vx_i8m8_m(vbool1_t mask, vint8m8_t op1, int8_t op2, size_t vl) {
+ return __riscv_vadd_vx_i8m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i16mf4_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s16i>, !cir.vector<[1] x !s16i>, !cir.vector<[1] x !s16i>, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vadd_vv_i16mf4_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
+//
+vint16mf4_t test_vadd_vv_i16mf4_m(vbool64_t mask, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
+ return __riscv_vadd_vv_i16mf4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i16mf4_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s16i>, !cir.vector<[1] x !s16i>, !s16i, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vadd_vx_i16mf4_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
+//
+vint16mf4_t test_vadd_vx_i16mf4_m(vbool64_t mask, vint16mf4_t op1, int16_t op2, size_t vl) {
+ return __riscv_vadd_vx_i16mf4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i16mf2_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s16i>, !cir.vector<[2] x !s16i>, !cir.vector<[2] x !s16i>, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vadd_vv_i16mf2_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
+//
+vint16mf2_t test_vadd_vv_i16mf2_m(vbool32_t mask, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i16mf2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i16mf2_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s16i>, !cir.vector<[2] x !s16i>, !s16i, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vadd_vx_i16mf2_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
+//
+vint16mf2_t test_vadd_vx_i16mf2_m(vbool32_t mask, vint16mf2_t op1, int16_t op2, size_t vl) {
+ return __riscv_vadd_vx_i16mf2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i16m1_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s16i>, !cir.vector<[4] x !s16i>, !cir.vector<[4] x !s16i>, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vadd_vv_i16m1_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vadd_vv_i16m1_m(vbool16_t mask, vint16m1_t op1, vint16m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_i16m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i16m1_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s16i>, !cir.vector<[4] x !s16i>, !s16i, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vadd_vx_i16m1_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vadd_vx_i16m1_m(vbool16_t mask, vint16m1_t op1, int16_t op2, size_t vl) {
+ return __riscv_vadd_vx_i16m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i16m2_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s16i>, !cir.vector<[8] x !s16i>, !cir.vector<[8] x !s16i>, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vadd_vv_i16m2_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vint16m2_t test_vadd_vv_i16m2_m(vbool8_t mask, vint16m2_t op1, vint16m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i16m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i16m2_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s16i>, !cir.vector<[8] x !s16i>, !s16i, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vadd_vx_i16m2_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vint16m2_t test_vadd_vx_i16m2_m(vbool8_t mask, vint16m2_t op1, int16_t op2, size_t vl) {
+ return __riscv_vadd_vx_i16m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i16m4_m(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !s16i>, !cir.vector<[16] x !s16i>, !cir.vector<[16] x !s16i>, !cir.vector<[16] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vadd_vv_i16m4_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vint16m4_t test_vadd_vv_i16m4_m(vbool4_t mask, vint16m4_t op1, vint16m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_i16m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i16m4_m(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !s16i>, !cir.vector<[16] x !s16i>, !s16i, !cir.vector<[16] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vadd_vx_i16m4_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vint16m4_t test_vadd_vx_i16m4_m(vbool4_t mask, vint16m4_t op1, int16_t op2, size_t vl) {
+ return __riscv_vadd_vx_i16m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i16m8_m(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !s16i>, !cir.vector<[32] x !s16i>, !cir.vector<[32] x !s16i>, !cir.vector<[32] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vadd_vv_i16m8_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vint16m8_t test_vadd_vv_i16m8_m(vbool2_t mask, vint16m8_t op1, vint16m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_i16m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i16m8_m(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !s16i>, !cir.vector<[32] x !s16i>, !s16i, !cir.vector<[32] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vadd_vx_i16m8_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], i16 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vint16m8_t test_vadd_vx_i16m8_m(vbool2_t mask, vint16m8_t op1, int16_t op2, size_t vl) {
+ return __riscv_vadd_vx_i16m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i32mf2_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s32i>, !cir.vector<[1] x !s32i>, !cir.vector<[1] x !s32i>, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vadd_vv_i32mf2_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vadd_vv_i32mf2_m(vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i32mf2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i32mf2_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s32i>, !cir.vector<[1] x !s32i>, !s32i, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vadd_vx_i32mf2_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vadd_vx_i32mf2_m(vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
+ return __riscv_vadd_vx_i32mf2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i32m1_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s32i>, !cir.vector<[2] x !s32i>, !cir.vector<[2] x !s32i>, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vadd_vv_i32m1_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vadd_vv_i32m1_m(vbool32_t mask, vint32m1_t op1, vint32m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_i32m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i32m1_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s32i>, !cir.vector<[2] x !s32i>, !s32i, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vadd_vx_i32m1_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vadd_vx_i32m1_m(vbool32_t mask, vint32m1_t op1, int32_t op2, size_t vl) {
+ return __riscv_vadd_vx_i32m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i32m2_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s32i>, !cir.vector<[4] x !s32i>, !cir.vector<[4] x !s32i>, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vadd_vv_i32m2_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vadd_vv_i32m2_m(vbool16_t mask, vint32m2_t op1, vint32m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i32m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i32m2_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s32i>, !cir.vector<[4] x !s32i>, !s32i, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vadd_vx_i32m2_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vadd_vx_i32m2_m(vbool16_t mask, vint32m2_t op1, int32_t op2, size_t vl) {
+ return __riscv_vadd_vx_i32m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i32m4_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s32i>, !cir.vector<[8] x !s32i>, !cir.vector<[8] x !s32i>, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vadd_vv_i32m4_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vadd_vv_i32m4_m(vbool8_t mask, vint32m4_t op1, vint32m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_i32m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i32m4_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s32i>, !cir.vector<[8] x !s32i>, !s32i, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vadd_vx_i32m4_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vadd_vx_i32m4_m(vbool8_t mask, vint32m4_t op1, int32_t op2, size_t vl) {
+ return __riscv_vadd_vx_i32m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i32m8_m(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !s32i>, !cir.vector<[16] x !s32i>, !cir.vector<[16] x !s32i>, !cir.vector<[16] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vadd_vv_i32m8_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vadd_vv_i32m8_m(vbool4_t mask, vint32m8_t op1, vint32m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_i32m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i32m8_m(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !s32i>, !cir.vector<[16] x !s32i>, !s32i, !cir.vector<[16] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vadd_vx_i32m8_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], i32 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vadd_vx_i32m8_m(vbool4_t mask, vint32m8_t op1, int32_t op2, size_t vl) {
+ return __riscv_vadd_vx_i32m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i64m1_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s64i>, !cir.vector<[1] x !s64i>, !cir.vector<[1] x !s64i>, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vadd_vv_i64m1_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vadd_vv_i64m1_m(vbool64_t mask, vint64m1_t op1, vint64m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_i64m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i64m1_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !s64i>, !cir.vector<[1] x !s64i>, !s64i, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vadd_vx_i64m1_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vadd_vx_i64m1_m(vbool64_t mask, vint64m1_t op1, int64_t op2, size_t vl) {
+ return __riscv_vadd_vx_i64m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i64m2_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s64i>, !cir.vector<[2] x !s64i>, !cir.vector<[2] x !s64i>, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vadd_vv_i64m2_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vint64m2_t test_vadd_vv_i64m2_m(vbool32_t mask, vint64m2_t op1, vint64m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_i64m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i64m2_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !s64i>, !cir.vector<[2] x !s64i>, !s64i, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vadd_vx_i64m2_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vint64m2_t test_vadd_vx_i64m2_m(vbool32_t mask, vint64m2_t op1, int64_t op2, size_t vl) {
+ return __riscv_vadd_vx_i64m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i64m4_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s64i>, !cir.vector<[4] x !s64i>, !cir.vector<[4] x !s64i>, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vadd_vv_i64m4_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vint64m4_t test_vadd_vv_i64m4_m(vbool16_t mask, vint64m4_t op1, vint64m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_i64m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i64m4_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !s64i>, !cir.vector<[4] x !s64i>, !s64i, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vadd_vx_i64m4_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vint64m4_t test_vadd_vx_i64m4_m(vbool16_t mask, vint64m4_t op1, int64_t op2, size_t vl) {
+ return __riscv_vadd_vx_i64m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_i64m8_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s64i>, !cir.vector<[8] x !s64i>, !cir.vector<[8] x !s64i>, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vadd_vv_i64m8_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vint64m8_t test_vadd_vv_i64m8_m(vbool8_t mask, vint64m8_t op1, vint64m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_i64m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_i64m8_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !s64i>, !cir.vector<[8] x !s64i>, !s64i, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vadd_vx_i64m8_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], i64 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vint64m8_t test_vadd_vx_i64m8_m(vbool8_t mask, vint64m8_t op1, int64_t op2, size_t vl) {
+ return __riscv_vadd_vx_i64m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8mf8_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u8i>, !cir.vector<[1] x !u8i>, !cir.vector<[1] x !u8i>, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vadd_vv_u8mf8_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], <vscale x 1 x i8> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8mf8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8mf8_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u8i>, !cir.vector<[1] x !u8i>, !u8i, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vadd_vx_u8mf8_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> [[OP1]], i8 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8mf8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8mf4_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u8i>, !cir.vector<[2] x !u8i>, !cir.vector<[2] x !u8i>, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vadd_vv_u8mf4_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], <vscale x 2 x i8> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
+//
+vuint8mf4_t test_vadd_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8mf4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8mf4_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u8i>, !cir.vector<[2] x !u8i>, !u8i, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vadd_vx_u8mf4_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> [[OP1]], i8 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
+//
+vuint8mf4_t test_vadd_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8mf4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8mf2_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u8i>, !cir.vector<[4] x !u8i>, !cir.vector<[4] x !u8i>, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vadd_vv_u8mf2_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], <vscale x 4 x i8> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
+//
+vuint8mf2_t test_vadd_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8mf2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8mf2_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u8i>, !cir.vector<[4] x !u8i>, !u8i, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vadd_vx_u8mf2_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> [[OP1]], i8 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
+//
+vuint8mf2_t test_vadd_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8mf2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8m1_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u8i>, !cir.vector<[8] x !u8i>, !cir.vector<[8] x !u8i>, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vadd_vv_u8m1_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], <vscale x 8 x i8> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vadd_vv_u8m1_m(vbool8_t mask, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8m1_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u8i>, !cir.vector<[8] x !u8i>, !u8i, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vadd_vx_u8m1_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[OP1]], i8 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vadd_vx_u8m1_m(vbool8_t mask, vuint8m1_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8m2_m(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !u8i>, !cir.vector<[16] x !u8i>, !cir.vector<[16] x !u8i>, !cir.vector<[16] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vadd_vv_u8m2_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], <vscale x 16 x i8> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vuint8m2_t test_vadd_vv_u8m2_m(vbool4_t mask, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8m2_m(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !u8i>, !cir.vector<[16] x !u8i>, !u8i, !cir.vector<[16] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vadd_vx_u8m2_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> [[OP1]], i8 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vuint8m2_t test_vadd_vx_u8m2_m(vbool4_t mask, vuint8m2_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8m4_m(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !u8i>, !cir.vector<[32] x !u8i>, !cir.vector<[32] x !u8i>, !cir.vector<[32] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vadd_vv_u8m4_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], <vscale x 32 x i8> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vuint8m4_t test_vadd_vv_u8m4_m(vbool2_t mask, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8m4_m(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !u8i>, !cir.vector<[32] x !u8i>, !u8i, !cir.vector<[32] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vadd_vx_u8m4_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> [[OP1]], i8 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vuint8m4_t test_vadd_vx_u8m4_m(vbool2_t mask, vuint8m4_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u8m8_m(
+// CIR-SAME: -> !cir.vector<[64]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[64] x !u8i>, !cir.vector<[64] x !u8i>, !cir.vector<[64] x !u8i>, !cir.vector<[64] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[64]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vadd_vv_u8m8_m
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], <vscale x 64 x i8> [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vuint8m8_t test_vadd_vv_u8m8_m(vbool1_t mask, vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_u8m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u8m8_m(
+// CIR-SAME: -> !cir.vector<[64]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[64] x !u8i>, !cir.vector<[64] x !u8i>, !u8i, !cir.vector<[64] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[64]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vadd_vx_u8m8_m
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> [[OP1]], i8 [[OP2]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vuint8m8_t test_vadd_vx_u8m8_m(vbool1_t mask, vuint8m8_t op1, uint8_t op2, size_t vl) {
+ return __riscv_vadd_vx_u8m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u16mf4_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u16i>, !cir.vector<[1] x !u16i>, !cir.vector<[1] x !u16i>, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vadd_vv_u16mf4_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], <vscale x 1 x i16> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
+//
+vuint16mf4_t test_vadd_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
+ return __riscv_vadd_vv_u16mf4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u16mf4_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u16i>, !cir.vector<[1] x !u16i>, !u16i, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vadd_vx_u16mf4_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> [[OP1]], i16 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
+//
+vuint16mf4_t test_vadd_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t op1, uint16_t op2, size_t vl) {
+ return __riscv_vadd_vx_u16mf4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u16mf2_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u16i>, !cir.vector<[2] x !u16i>, !cir.vector<[2] x !u16i>, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vadd_vv_u16mf2_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], <vscale x 2 x i16> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
+//
+vuint16mf2_t test_vadd_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u16mf2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u16mf2_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u16i>, !cir.vector<[2] x !u16i>, !u16i, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vadd_vx_u16mf2_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> [[OP1]], i16 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
+//
+vuint16mf2_t test_vadd_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t op1, uint16_t op2, size_t vl) {
+ return __riscv_vadd_vx_u16mf2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u16m1_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u16i>, !cir.vector<[4] x !u16i>, !cir.vector<[4] x !u16i>, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vadd_vv_u16m1_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], <vscale x 4 x i16> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vadd_vv_u16m1_m(vbool16_t mask, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_u16m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u16m1_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u16i>, !cir.vector<[4] x !u16i>, !u16i, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vadd_vx_u16m1_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> [[OP1]], i16 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vadd_vx_u16m1_m(vbool16_t mask, vuint16m1_t op1, uint16_t op2, size_t vl) {
+ return __riscv_vadd_vx_u16m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u16m2_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u16i>, !cir.vector<[8] x !u16i>, !cir.vector<[8] x !u16i>, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vadd_vv_u16m2_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], <vscale x 8 x i16> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vuint16m2_t test_vadd_vv_u16m2_m(vbool8_t mask, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u16m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u16m2_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u16i>, !cir.vector<[8] x !u16i>, !u16i, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vadd_vx_u16m2_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> [[OP1]], i16 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vuint16m2_t test_vadd_vx_u16m2_m(vbool8_t mask, vuint16m2_t op1, uint16_t op2, size_t vl) {
+ return __riscv_vadd_vx_u16m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u16m4_m(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !u16i>, !cir.vector<[16] x !u16i>, !cir.vector<[16] x !u16i>, !cir.vector<[16] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vadd_vv_u16m4_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], <vscale x 16 x i16> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vuint16m4_t test_vadd_vv_u16m4_m(vbool4_t mask, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_u16m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u16m4_m(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !u16i>, !cir.vector<[16] x !u16i>, !u16i, !cir.vector<[16] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vadd_vx_u16m4_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> [[OP1]], i16 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vuint16m4_t test_vadd_vx_u16m4_m(vbool4_t mask, vuint16m4_t op1, uint16_t op2, size_t vl) {
+ return __riscv_vadd_vx_u16m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u16m8_m(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !u16i>, !cir.vector<[32] x !u16i>, !cir.vector<[32] x !u16i>, !cir.vector<[32] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vadd_vv_u16m8_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], <vscale x 32 x i16> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vuint16m8_t test_vadd_vv_u16m8_m(vbool2_t mask, vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_u16m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u16m8_m(
+// CIR-SAME: -> !cir.vector<[32]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[32] x !u16i>, !cir.vector<[32] x !u16i>, !u16i, !cir.vector<[32] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[32]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vadd_vx_u16m8_m
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 noundef{{( zeroext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> [[OP1]], i16 [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vuint16m8_t test_vadd_vx_u16m8_m(vbool2_t mask, vuint16m8_t op1, uint16_t op2, size_t vl) {
+ return __riscv_vadd_vx_u16m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u32mf2_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u32i>, !cir.vector<[1] x !u32i>, !cir.vector<[1] x !u32i>, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vadd_vv_u32mf2_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], <vscale x 1 x i32> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vadd_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u32mf2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u32mf2_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u32i>, !cir.vector<[1] x !u32i>, !u32i, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vadd_vx_u32mf2_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> [[OP1]], i32 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vadd_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
+ return __riscv_vadd_vx_u32mf2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u32m1_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u32i>, !cir.vector<[2] x !u32i>, !cir.vector<[2] x !u32i>, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vadd_vv_u32m1_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], <vscale x 2 x i32> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vadd_vv_u32m1_m(vbool32_t mask, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_u32m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u32m1_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u32i>, !cir.vector<[2] x !u32i>, !u32i, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vadd_vx_u32m1_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1]], i32 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vadd_vx_u32m1_m(vbool32_t mask, vuint32m1_t op1, uint32_t op2, size_t vl) {
+ return __riscv_vadd_vx_u32m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u32m2_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u32i>, !cir.vector<[4] x !u32i>, !cir.vector<[4] x !u32i>, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vadd_vv_u32m2_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], <vscale x 4 x i32> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_vadd_vv_u32m2_m(vbool16_t mask, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u32m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u32m2_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u32i>, !cir.vector<[4] x !u32i>, !u32i, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vadd_vx_u32m2_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> [[OP1]], i32 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_vadd_vx_u32m2_m(vbool16_t mask, vuint32m2_t op1, uint32_t op2, size_t vl) {
+ return __riscv_vadd_vx_u32m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u32m4_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u32i>, !cir.vector<[8] x !u32i>, !cir.vector<[8] x !u32i>, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vadd_vv_u32m4_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], <vscale x 8 x i32> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_vadd_vv_u32m4_m(vbool8_t mask, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_u32m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u32m4_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u32i>, !cir.vector<[8] x !u32i>, !u32i, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vadd_vx_u32m4_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> [[OP1]], i32 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_vadd_vx_u32m4_m(vbool8_t mask, vuint32m4_t op1, uint32_t op2, size_t vl) {
+ return __riscv_vadd_vx_u32m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u32m8_m(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !u32i>, !cir.vector<[16] x !u32i>, !cir.vector<[16] x !u32i>, !cir.vector<[16] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vadd_vv_u32m8_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], <vscale x 16 x i32> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vuint32m8_t test_vadd_vv_u32m8_m(vbool4_t mask, vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_u32m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u32m8_m(
+// CIR-SAME: -> !cir.vector<[16]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[16] x !u32i>, !cir.vector<[16] x !u32i>, !u32i, !cir.vector<[16] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[16]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vadd_vx_u32m8_m
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 noundef{{( signext)?}} [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> [[OP1]], i32 [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vuint32m8_t test_vadd_vx_u32m8_m(vbool4_t mask, vuint32m8_t op1, uint32_t op2, size_t vl) {
+ return __riscv_vadd_vx_u32m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u64m1_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u64i>, !cir.vector<[1] x !u64i>, !cir.vector<[1] x !u64i>, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vadd_vv_u64m1_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], <vscale x 1 x i64> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vadd_vv_u64m1_m(vbool64_t mask, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
+ return __riscv_vadd_vv_u64m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u64m1_m(
+// CIR-SAME: -> !cir.vector<[1]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[1] x !u64i>, !cir.vector<[1] x !u64i>, !u64i, !cir.vector<[1] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[1]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vadd_vx_u64m1_m
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> [[OP1]], i64 [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vadd_vx_u64m1_m(vbool64_t mask, vuint64m1_t op1, uint64_t op2, size_t vl) {
+ return __riscv_vadd_vx_u64m1_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u64m2_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u64i>, !cir.vector<[2] x !u64i>, !cir.vector<[2] x !u64i>, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vadd_vv_u64m2_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], <vscale x 2 x i64> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vuint64m2_t test_vadd_vv_u64m2_m(vbool32_t mask, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
+ return __riscv_vadd_vv_u64m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u64m2_m(
+// CIR-SAME: -> !cir.vector<[2]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[2] x !u64i>, !cir.vector<[2] x !u64i>, !u64i, !cir.vector<[2] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[2]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vadd_vx_u64m2_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> [[OP1]], i64 [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vuint64m2_t test_vadd_vx_u64m2_m(vbool32_t mask, vuint64m2_t op1, uint64_t op2, size_t vl) {
+ return __riscv_vadd_vx_u64m2_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u64m4_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u64i>, !cir.vector<[4] x !u64i>, !cir.vector<[4] x !u64i>, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vadd_vv_u64m4_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], <vscale x 4 x i64> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vuint64m4_t test_vadd_vv_u64m4_m(vbool16_t mask, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
+ return __riscv_vadd_vv_u64m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u64m4_m(
+// CIR-SAME: -> !cir.vector<[4]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[4] x !u64i>, !cir.vector<[4] x !u64i>, !u64i, !cir.vector<[4] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[4]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vadd_vx_u64m4_m
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> [[OP1]], i64 [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vuint64m4_t test_vadd_vx_u64m4_m(vbool16_t mask, vuint64m4_t op1, uint64_t op2, size_t vl) {
+ return __riscv_vadd_vx_u64m4_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vv_u64m8_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u64i>, !cir.vector<[8] x !u64i>, !cir.vector<[8] x !u64i>, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vadd_vv_u64m8_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], <vscale x 8 x i64> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vuint64m8_t test_vadd_vv_u64m8_m(vbool8_t mask, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
+ return __riscv_vadd_vv_u64m8_m(mask, op1, op2, vl);
+}
+
+// CIR-LABEL: cir.func{{.*}} @test_vadd_vx_u64m8_m(
+// CIR-SAME: -> !cir.vector<[8]
+// CIR: {{%.*}} = cir.call_llvm_intrinsic "riscv.vadd.mask" {{%.*}}, {{%.*}}, {{%.*}}, {{%.*}} : (!cir.vector<[8] x !u64i>, !cir.vector<[8] x !u64i>, !u64i, !cir.vector<[8] x !cir.int<u, 1>>, !u64i, !u64i) -> !cir.vector<[8]
+//
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vadd_vx_u64m8_m
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 noundef [[OP2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> [[OP1]], i64 [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 {{[03]}})
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vuint64m8_t test_vadd_vx_u64m8_m(vbool8_t mask, vuint64m8_t op1, uint64_t op2, size_t vl) {
+ return __riscv_vadd_vx_u64m8_m(mask, op1, op2, vl);
+}
+
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
index 95b7e71b060ab..ae6f4d7cae65f 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -110,6 +110,10 @@ class RVVEmitter {
/// Emit all the information needed to map builtin -> LLVM IR intrinsic.
void createCodeGen(raw_ostream &o);
+ /// Emit all the information needed to map builtin -> LLVM IR intrinsic for
+ /// the CIR codegen path.
+ void createCIRCodeGen(raw_ostream &o);
+
/// Emit all the information needed by SemaRISCVVectorLookup.cpp.
/// We've large number of intrinsic function for RVV, creating a customized
/// could speed up the compilation time.
@@ -324,6 +328,62 @@ void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
OS << " break;\n";
}
+void emitCIRCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
+ if (!RVVI->getIRName().empty()) {
+ std::string IRName = RVVI->getIRName().str();
+ if (RVVI->isMasked())
+ IRName = StringRef(IRName).rsplit("_mask").first.str() + ".mask";
+ OS << " intrinsicName = \"riscv." << IRName << "\";\n";
+ }
+
+ if (RVVI->hasManualCodegen()) {
+ OS << " hasCirManualCodegen = true;\n";
+ OS << " break;\n";
+ return;
+ }
+
+ OS << " hasCirManualCodegen = false;\n";
+
+ for (const auto &I : enumerate(RVVI->getInputTypes())) {
+ if (I.value()->isPointer()) {
+ assert(RVVI->getIntrinsicTypes().front() == -1 &&
+ "RVVI should be vector load intrinsic.");
+ }
+ }
+
+ if (RVVI->isMasked()) {
+ if (RVVI->hasVL()) {
+ OS << " std::rotate(ops.begin(), ops.begin() + 1, ops.end() - 1);\n";
+ if (RVVI->hasPolicyOperand())
+ OS << " ops.push_back(getBuilder().getConstInt(loc, "
+ "ops.back().getType(),"
+ " PolicyAttrs));\n";
+ if (RVVI->hasMaskedOffOperand() && RVVI->getPolicyAttrs().isTAMAPolicy())
+ OS << " ops.insert(ops.begin(), "
+ "getBuilder().getConstant(loc, "
+ "cir::PoisonAttr::get(returnType)));\n";
+ if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
+ RVVI->getPolicyAttrs().isTAMAPolicy())
+ OS << " ops.insert(ops.begin(), "
+ "getBuilder().getConstant(loc, "
+ "cir::PoisonAttr::get(returnType)));\n";
+ } else {
+ OS << " std::rotate(ops.begin(), ops.begin() + 1, ops.end());\n";
+ }
+ } else {
+ if (RVVI->hasPolicyOperand())
+ OS << " ops.push_back(getBuilder().getConstInt(loc, "
+ "ops.back().getType(), "
+ "PolicyAttrs));\n";
+ else if (RVVI->hasPassthruOperand() && RVVI->getPolicyAttrs().isTAPolicy())
+ OS << " ops.insert(ops.begin(), "
+ "getBuilder().getConstant(loc, "
+ "cir::PoisonAttr::get(returnType)));\n";
+ }
+
+ OS << " break;\n";
+}
+
//===----------------------------------------------------------------------===//
// SemaSignatureTable implementation
//===----------------------------------------------------------------------===//
@@ -646,6 +706,54 @@ void RVVEmitter::createCodeGen(raw_ostream &OS) {
OS << "\n";
}
+void RVVEmitter::createCIRCodeGen(raw_ostream &OS) {
+ std::vector<std::unique_ptr<RVVIntrinsic>> Defs;
+ createRVVIntrinsics(Defs);
+ stable_sort(Defs, [](const std::unique_ptr<RVVIntrinsic> &A,
+ const std::unique_ptr<RVVIntrinsic> &B) {
+ if (A->getIRName() == B->getIRName())
+ return (A->getPolicyAttrs() < B->getPolicyAttrs());
+ return (A->getIRName() < B->getIRName());
+ });
+
+ // Map to keep track of which builtin names have already been emitted.
+ StringMap<RVVIntrinsic *> BuiltinMap;
+
+ // Print switch body when the ir name or ManualCodegen changes from
+ // previous iteration.
+ RVVIntrinsic *PrevDef = Defs.begin()->get();
+ for (auto &Def : Defs) {
+ StringRef CurIRName = Def->getIRName();
+ if (CurIRName != PrevDef->getIRName() ||
+ (Def->getManualCodegen() != PrevDef->getManualCodegen()) ||
+ (Def->getPolicyAttrs() != PrevDef->getPolicyAttrs())) {
+ emitCIRCodeGenSwitchBody(PrevDef, OS);
+ }
+ PrevDef = Def.get();
+
+ auto P =
+ BuiltinMap.insert(std::make_pair(Def->getBuiltinName(), Def.get()));
+ if (P.second) {
+ OS << "case RISCVVector::BI__builtin_rvv_" << Def->getBuiltinName()
+ << ":\n";
+ continue;
+ }
+
+ if (P.first->second->getIRName() != Def->getIRName())
+ PrintFatalError("Builtin with same name has different IRName");
+ else if (P.first->second->getManualCodegen() != Def->getManualCodegen())
+ PrintFatalError("Builtin with same name has different ManualCodegen");
+ else if (P.first->second->isMasked() != Def->isMasked())
+ PrintFatalError("Builtin with same name has different isMasked");
+ else if (P.first->second->hasVL() != Def->hasVL())
+ PrintFatalError("Builtin with same name has different hasVL");
+ else if (P.first->second->getPolicyScheme() != Def->getPolicyScheme())
+ PrintFatalError("Builtin with same name has different getPolicyScheme");
+ }
+ emitCIRCodeGenSwitchBody(Defs.back().get(), OS);
+ OS << "\n";
+}
+
void RVVEmitter::createRVVIntrinsics(
std::vector<std::unique_ptr<RVVIntrinsic>> &Out,
std::vector<SemaRecord> *SemaRecords) {
@@ -905,6 +1013,10 @@ void EmitRVVBuiltinCG(const RecordKeeper &Records, raw_ostream &OS) {
RVVEmitter(Records).createCodeGen(OS);
}
+void EmitRVVBuiltinCIRCG(const RecordKeeper &Records, raw_ostream &OS) {
+ RVVEmitter(Records).createCIRCodeGen(OS);
+}
+
void EmitRVVBuiltinSema(const RecordKeeper &Records, raw_ostream &OS) {
RVVEmitter(Records).createSema(OS);
}
diff --git a/clang/utils/TableGen/TableGen.cpp b/clang/utils/TableGen/TableGen.cpp
index 0ce9d8306ae16..a4391f8018185 100644
--- a/clang/utils/TableGen/TableGen.cpp
+++ b/clang/utils/TableGen/TableGen.cpp
@@ -111,6 +111,7 @@ enum ActionType {
GenRISCVVectorHeader,
GenRISCVVectorBuiltins,
GenRISCVVectorBuiltinCG,
+ GenRISCVVectorBuiltinCIRCG,
GenRISCVVectorBuiltinSema,
GenRISCVSiFiveVectorBuiltins,
GenRISCVSiFiveVectorBuiltinCG,
@@ -328,6 +329,9 @@ cl::opt<ActionType> Action(
"Generate riscv_vector_builtins.inc for clang"),
clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
"Generate riscv_vector_builtin_cg.inc for clang"),
+ clEnumValN(GenRISCVVectorBuiltinCIRCG,
+ "gen-riscv-vector-builtin-cir-codegen",
+ "Generate riscv_vector_builtin_cir_cg.inc for clang"),
clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
"Generate riscv_vector_builtin_sema.inc for clang"),
clEnumValN(GenRISCVSiFiveVectorBuiltins,
@@ -641,6 +645,9 @@ bool ClangTableGenMain(raw_ostream &OS, const RecordKeeper &Records) {
case GenRISCVVectorBuiltinCG:
EmitRVVBuiltinCG(Records, OS);
break;
+ case GenRISCVVectorBuiltinCIRCG:
+ EmitRVVBuiltinCIRCG(Records, OS);
+ break;
case GenRISCVVectorBuiltinSema:
EmitRVVBuiltinSema(Records, OS);
break;
diff --git a/clang/utils/TableGen/TableGenBackends.h b/clang/utils/TableGen/TableGenBackends.h
index f9bd7ccf9d0d8..057bf1ed51f04 100644
--- a/clang/utils/TableGen/TableGenBackends.h
+++ b/clang/utils/TableGen/TableGenBackends.h
@@ -179,6 +179,8 @@ void EmitMveBuiltinAliases(const llvm::RecordKeeper &Records,
void EmitRVVHeader(const llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
void EmitRVVBuiltins(const llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
void EmitRVVBuiltinCG(const llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVBuiltinCIRCG(const llvm::RecordKeeper &Records,
+ llvm::raw_ostream &OS);
void EmitRVVBuiltinSema(const llvm::RecordKeeper &Records,
llvm::raw_ostream &OS);
>From e7216524469bd284e33d3af6747c89acf7902f2e Mon Sep 17 00:00:00 2001
From: Jianjian GUAN <jacquesguan at me.com>
Date: Fri, 5 Jun 2026 14:57:47 +0800
Subject: [PATCH 2/2] Address comment
---
clang/include/clang/Basic/CMakeLists.txt | 8 +++++---
clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp | 2 +-
clang/utils/TableGen/RISCVVEmitter.cpp | 5 +++--
3 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/clang/include/clang/Basic/CMakeLists.txt b/clang/include/clang/Basic/CMakeLists.txt
index b7e8b0d185667..6e670a06f01d6 100644
--- a/clang/include/clang/Basic/CMakeLists.txt
+++ b/clang/include/clang/Basic/CMakeLists.txt
@@ -226,9 +226,11 @@ clang_tablegen(riscv_vector_builtins.inc -gen-riscv-vector-builtins
clang_tablegen(riscv_vector_builtin_cg.inc -gen-riscv-vector-builtin-codegen
SOURCE riscv_vector.td
TARGET ClangRISCVVectorBuiltinCG)
-clang_tablegen(riscv_vector_builtin_cir_cg.inc -gen-riscv-vector-builtin-cir-codegen
- SOURCE riscv_vector.td
- TARGET ClangRISCVVectorBuiltinCIRCG)
+if(CLANG_ENABLE_CIR)
+ clang_tablegen(riscv_vector_builtin_cir_cg.inc -gen-riscv-vector-builtin-cir-codegen
+ SOURCE riscv_vector.td
+ TARGET ClangRISCVVectorBuiltinCIRCG)
+endif()
clang_tablegen(riscv_vector_builtin_sema.inc -gen-riscv-vector-builtin-sema
SOURCE riscv_vector.td
TARGET ClangRISCVVectorBuiltinSema)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
index 10119a5a6dcbc..81d2cac37e2e9 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
@@ -64,7 +64,7 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
// TODO: Handle ManualCodegen.
bool hasCirManualCodegen = false;
- int PolicyAttrs = 0;
+ int policyAttrs = 0;
switch (builtinID) {
default:
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
index ae6f4d7cae65f..9b7eb9d82c316 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -343,6 +343,7 @@ void emitCIRCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
}
OS << " hasCirManualCodegen = false;\n";
+ OS << " policyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
for (const auto &I : enumerate(RVVI->getInputTypes())) {
if (I.value()->isPointer()) {
@@ -357,7 +358,7 @@ void emitCIRCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
if (RVVI->hasPolicyOperand())
OS << " ops.push_back(getBuilder().getConstInt(loc, "
"ops.back().getType(),"
- " PolicyAttrs));\n";
+ " policyAttrs));\n";
if (RVVI->hasMaskedOffOperand() && RVVI->getPolicyAttrs().isTAMAPolicy())
OS << " ops.insert(ops.begin(), "
"getBuilder().getConstant(loc, "
@@ -374,7 +375,7 @@ void emitCIRCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
if (RVVI->hasPolicyOperand())
OS << " ops.push_back(getBuilder().getConstInt(loc, "
"ops.back().getType(), "
- "PolicyAttrs));\n";
+ "policyAttrs));\n";
else if (RVVI->hasPassthruOperand() && RVVI->getPolicyAttrs().isTAPolicy())
OS << " ops.insert(ops.begin(), "
"getBuilder().getConstant(loc, "
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