[clang] [CIR][RISCV] Support vector buitlins codegen (PR #199889)

[Pengcheng Wang via cfe-commits]

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@@ -324,6 +328,62 @@ void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
   OS << "  break;\n";
 }
 
+void emitCIRCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
+  if (!RVVI->getIRName().empty()) {
+    std::string IRName = RVVI->getIRName().str();
+    if (RVVI->isMasked())
+      IRName = StringRef(IRName).rsplit("_mask").first.str() + ".mask";
+    OS << "  intrinsicName = \"riscv." << IRName << "\";\n";
+  }
+
+  if (RVVI->hasManualCodegen()) {
+    OS << "  hasCirManualCodegen = true;\n";
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wangpc-pp wrote:

We need to write two `ManualCodegen`s? One for Clang AST and one for CIR?

https://github.com/llvm/llvm-project/pull/199889