[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

[sstwcw via Phabricator via cfe-commits]

sstwcw updated this revision to Diff 510244.
sstwcw marked 2 inline comments as done.
sstwcw added a comment.

- Use shorter conditions


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147327/new/

https://reviews.llvm.org/D147327

Files:
  clang/docs/ClangFormatStyleOptions.rst
  clang/include/clang/Format/Format.h
  clang/lib/Format/Format.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/unittests/Format/ConfigParseTest.cpp
  clang/unittests/Format/FormatTestVerilog.cpp
  clang/unittests/Format/TokenAnnotatorTest.cpp

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