[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

[Björn Schäpers via Phabricator via cfe-commits]

HazardyKnusperkeks requested changes to this revision.
HazardyKnusperkeks added inline comments.
This revision now requires changes to proceed.


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Comment at: clang/include/clang/Format/Format.h:4185
+  /// For Verilog, put each port on its own line in module instantiations.
+  /// \code
+  ///    ffnand ff1(.q(),
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Can you put the true vs. false in the doc, like on other options?


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Comment at: clang/include/clang/Format/Format.h:4192
+  /// \version 17
+  bool VerilogBreakBetweenInstancePorts;
+
----------------
V after U


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Comment at: clang/lib/Format/TokenAnnotator.cpp:1150
+      if (Style.isVerilog()) {
+        const FormatToken *Prev = Tok->getPreviousNonComment(), *Prev2;
+        // Identify the parameter list and port list in a module instantiation.
----------------



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Comment at: clang/lib/Format/TokenAnnotator.cpp:1156-1163
+        if (Prev && (Prev2 = Prev->getPreviousNonComment()) &&
+            ((Prev->is(tok::hash) && Keywords.isVerilogIdentifier(*Prev2)) ||
+             (Keywords.isVerilogIdentifier(*Prev) &&
+              (Prev2->is(tok::r_paren) ||
+               Keywords.isVerilogIdentifier(*Prev2) ||
+               (Prev2->endsSequence(tok::comma, tok::r_paren) &&
+                (Prev2 = Prev2->getPreviousNonComment()->MatchingParen) &&
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I won't read that.

I think you should go with multiple if statements.


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  https://reviews.llvm.org/D147327/new/

https://reviews.llvm.org/D147327