[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

[Owen Pan via Phabricator via cfe-commits]

owenpan added inline comments.


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Comment at: clang/lib/Format/TokenAnnotator.cpp:1149-1191
+      if (Style.isVerilog()) {
+        const FormatToken *Prev = Tok->getPreviousNonComment();
+        const FormatToken *PrevPrev;
+        // Identify the parameter list and port list in a module instantiation.
+        // This is still needed when we already have
+        // UnwrappedLineParser::parseVerilogHierarchyHeader because that
+        // function is only responsible for the definition, not the
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Can you make it a function or lambda with early returns?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147327/new/

https://reviews.llvm.org/D147327