[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.


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Comment at: flang/test/Driver/target-cpu-features-invalid.f90:13
+! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor)
+! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this target (ignoring feature)
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awarzynski wrote:
> jrtc27 wrote:
> > Don't these come from the backend? Testing them here doesn't seem right...
> > Don't these come from the backend?
> 
> No. Both options are defined in Clang's Options.td:
> * [[ https://github.com/llvm/llvm-project/blob/0aac9a2875bad4f065367e4a6553fad78605f895/clang/include/clang/Driver/Options.td#L5251-L5253 | -target-feaure ]]
> * [[ https://github.com/llvm/llvm-project/blob/0aac9a2875bad4f065367e4a6553fad78605f895/clang/include/clang/Driver/Options.td#L5248-L5250 | -target-cpu ]]
Then why do they need aarch64-registered-target? Either they're coming from the backend and so you need the backend, or they're coming from the frontend and so you don't need the backend.


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https://reviews.llvm.org/D145883