[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

Mon Mar 13 13:04:19 PDT 2023

awarzynski accepted this revision.
awarzynski added a comment.
This revision is now accepted and ready to land.

LGTM, thanks for contributing!

Please wait for the other reviewers to confirm that they are happy with these changes.

================
Comment at: flang/test/Driver/target-cpu-features-invalid.f90:13
+! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor)
+! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this target (ignoring feature)
----------------
jrtc27 wrote:
> Don't these come from the backend? Testing them here doesn't seem right...
> Don't these come from the backend?

No. Both options are defined in Clang's Options.td:
* [[ https://github.com/llvm/llvm-project/blob/0aac9a2875bad4f065367e4a6553fad78605f895/clang/include/clang/Driver/Options.td#L5251-L5253 | -target-feaure ]]
* [[ https://github.com/llvm/llvm-project/blob/0aac9a2875bad4f065367e4a6553fad78605f895/clang/include/clang/Driver/Options.td#L5248-L5250 | -target-cpu ]]

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145883/new/

https://reviews.llvm.org/D145883