[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

Mon Mar 13 12:51:55 PDT 2023

sunshaoce added inline comments.

================
Comment at: flang/test/Driver/code-gen-rv64.f90:7
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
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awarzynski wrote:
> jrtc27 wrote:
> > Why do we need to go to an object file??? That's terrible practice in Clang tests, and the same should be true of Flang. Test the IR, that is sufficient, and decouples you from the backend.
> > That's terrible practice in Clang tests, and the same should be true of Flang. Test the IR, that is sufficient, and decouples you from the backend.
> 
> I disagree. 
> 
> A compiler driver is responsible for creating a correct backend/LLVM invocation. Is there some other way to verify that the backend invocation is correct? (other then inspecting the generated machine code file).
> 
> I agree that it is desirable to avoid any architectural details leaking outside of LLVM (into e.g. Clang and/or Flang), but IMHO it's very hard to avoid in practice.
After my test, there is no difference between the LLVM IR generated before and after modification. These tests are also from or similar to those that already exist.

So I think we can land this patch first. Then fix these in a new patch.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145883/new/

https://reviews.llvm.org/D145883