[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

[MyDeveloperDay via Phabricator via cfe-commits]

MyDeveloperDay accepted this revision.
MyDeveloperDay added a comment.
This revision is now accepted and ready to land.

Thank you for adding the tests, as I don't know Verilog then I can't really comment on the correctness, as you are mostly in your own scoped verilog functions, I'm fine with you improving the Verilog support, I don't personally see anything wrong with the touch points with other languages. I'm not sure if others have comments or if they have expertise in this area.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143825/new/

https://reviews.llvm.org/D143825