[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

[Owen Pan via Phabricator via cfe-commits]

owenpan added inline comments.


================
Comment at: clang/lib/Format/TokenAnnotator.cpp:2665
+    if (Style.isVerilog() && Precedence == prec::Comma &&
+        VerilogFirstOfType != nullptr) {
+      addFakeParenthesis(VerilogFirstOfType, prec::Comma);
----------------
And other places as well.


================
Comment at: clang/lib/Format/TokenAnnotator.cpp:2808
+                                FormatToken *PreviousComma) {
+    if (Current == nullptr)
+      return nullptr;
----------------
And other places too.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143825/new/

https://reviews.llvm.org/D143825