[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

[sstwcw via Phabricator via cfe-commits]

sstwcw updated this revision to Diff 498376.
sstwcw marked 3 inline comments as done.
sstwcw added a comment.

- add tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143825/new/

https://reviews.llvm.org/D143825

Files:
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/unittests/Format/FormatTestVerilog.cpp

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