[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

sstwcw via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Fri Feb 17 07:54:11 PST 2023


sstwcw marked 3 inline comments as done.
sstwcw added inline comments.


================
Comment at: clang/lib/Format/TokenAnnotator.cpp:2836
+          Tok = Tok->getNextNonComment();
+      } else if (Tok->is(tok::hashhash)) {
+        // Concatenation. Skip.
----------------
MyDeveloperDay wrote:
> are we covering these cases in the unit tests
I added a test on line 432.


================
Comment at: clang/lib/Format/TokenAnnotator.cpp:2846
+        // The name may have dots like `interface_foo.modport_foo`.
+        while (Tok != nullptr && Tok->isOneOf(tok::period, tok::coloncolon) &&
+               (Tok = Tok->getNextNonComment())) {
----------------
MyDeveloperDay wrote:
> are we covering these cases in the unit tests
I added a test on line 374.


================
Comment at: clang/lib/Format/TokenAnnotator.cpp:4365
+    if (Right.is(tok::l_paren) && Right.is(TT_VerilogStrength))
+      return true;
   }
----------------
MyDeveloperDay wrote:
> Is this an unrelated change? if not can you add an test
I added a test on line 255.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143825/new/

https://reviews.llvm.org/D143825



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