[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

[MyDeveloperDay via Phabricator via cfe-commits]

MyDeveloperDay added inline comments.


================
Comment at: clang/lib/Format/TokenAnnotator.cpp:2836
+          Tok = Tok->getNextNonComment();
+      } else if (Tok->is(tok::hashhash)) {
+        // Concatenation. Skip.
----------------
are we covering these cases in the unit tests


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Comment at: clang/lib/Format/TokenAnnotator.cpp:2846
+        // The name may have dots like `interface_foo.modport_foo`.
+        while (Tok != nullptr && Tok->isOneOf(tok::period, tok::coloncolon) &&
+               (Tok = Tok->getNextNonComment())) {
----------------
are we covering these cases in the unit tests


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Comment at: clang/lib/Format/TokenAnnotator.cpp:4365
+    if (Right.is(tok::l_paren) && Right.is(TT_VerilogStrength))
+      return true;
   }
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Is this an unrelated change? if not can you add an test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143825/new/

https://reviews.llvm.org/D143825