[PATCH] D136145: [IR][RFC] Restrict read only when cache type of llvm.prefetch is instruction

[Phoebe Wang via Phabricator via cfe-commits]

pengfei added a comment.

In D136145#3864584 <https://reviews.llvm.org/D136145#3864584>, @lenary wrote:

> The Arm changes (for tests) here are reasonable, and indeed both arm architectures do not allocate encoding space for instruction write.

Thanks @lenary for confirmation!


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D136145/new/

https://reviews.llvm.org/D136145