[PATCH] D136145: [IR][RFC] Restrict read only when cache type of llvm.prefetch is instruction

[Sam Elliott via Phabricator via cfe-commits]

lenary added a comment.

The Arm changes (for tests) here are reasonable, and indeed both arm architectures do not allocate encoding space for instruction write.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136145/new/

https://reviews.llvm.org/D136145