[PATCH] D136145: [IR][RFC] Restrict read only when cache type of llvm.prefetch is instruction

[Phoebe Wang via Phabricator via cfe-commits]

pengfei created this revision.
pengfei added reviewers: craig.topper, uweigand, lenary, efriedma.
Herald added subscribers: StephenFan, jdoerfert, hiraditya.
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pengfei requested review of this revision.
Herald added projects: clang, LLVM.
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LLVM backends like X86 always lowers prefetch intrinsics into similar
type if the desired one is not available.
For example, T2 hint -> T1 or write hint -> read. See llvm/test/CodeGen/X86/prefetch.ll
However, it's not clear for backend to choose between "write data" or "read
instruction" if there is no native "write instruction" instructions.
As far as I know, there's no upstream target that has supported "write
instruction" at the moment. So there should be no real impact by this
patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136145

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-arm.c
  clang/test/Sema/builtin-prefetch.c
  llvm/docs/LangRef.rst
  llvm/lib/IR/Verifier.cpp
  llvm/lib/Target/X86/X86Instr3DNow.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/test/CodeGen/SystemZ/prefetch-01.ll
  llvm/test/CodeGen/X86/prefetch.ll

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