[PATCH] D128712: [clang-format] Handle Verilog modules

[sstwcw via Phabricator via cfe-commits]

sstwcw created this revision.
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Now things inside hierarchies like modules and interfaces are
indented.  When the module header spans multiple lines, all except the
first line are indented as continuations.  We added the property
`IsContinuation` to mark lines that should be indented this way.

In order that the colons inside square brackets don't get labeled as
`TT_ObjCMethodExpr`, we added a check to only use this type when the
language is C#.  We used `isCpp` which returns true for C# and also when
the filename is not given and the program isn't sure what language it is
handling.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128712

Files:
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/lib/Format/TokenAnnotator.h
  clang/lib/Format/UnwrappedLineFormatter.cpp
  clang/lib/Format/UnwrappedLineParser.cpp
  clang/lib/Format/UnwrappedLineParser.h
  clang/unittests/Format/FormatTestVerilog.cpp
  clang/unittests/Format/TokenAnnotatorTest.cpp

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