[PATCH] D128712: [clang-format] Handle Verilog modules

[Björn Schäpers via Phabricator via cfe-commits]

HazardyKnusperkeks added inline comments.


================
Comment at: clang/lib/Format/FormatToken.h:1742
+  /// Returns whether \p Tok is a Verilog keyword that opens a module, etc.
+  bool isVerilogHier(const FormatToken &Tok) const {
+    if (Tok.endsSequence(kw_function, kw_with))
----------------
Please write it out.

For a german //hier// has a different meaning. ;)


================
Comment at: clang/lib/Format/TokenAnnotator.cpp:241
     bool StartsObjCMethodExpr = false;
-    if (FormatToken *MaybeSel = OpeningParen.Previous) {
-      // @selector( starts a selector.
-      if (MaybeSel->isObjCAtKeyword(tok::objc_selector) && MaybeSel->Previous &&
-          MaybeSel->Previous->is(tok::at)) {
-        StartsObjCMethodExpr = true;
+    if (Style.isCpp()) {
+      if (FormatToken *MaybeSel = OpeningParen.Previous) {
----------------
?

I don't know where this is also used.

Let's see what the others say.


================
Comment at: clang/lib/Format/TokenAnnotator.cpp:766
           CurrentToken->setType(TT_AttributeColon);
-        } else if (Left->isOneOf(TT_ArraySubscriptLSquare,
+        } else if (Style.isCpp() &&
+                   Left->isOneOf(TT_ArraySubscriptLSquare,
----------------
See above.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128712/new/

https://reviews.llvm.org/D128712