[PATCH] D124700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic
Stanislav Mekhanoshin via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Fri Apr 29 17:29:53 PDT 2022
rampitec accepted this revision.
rampitec added a comment.
This revision is now accepted and ready to land.
In D124700#3483715 <https://reviews.llvm.org/D124700#3483715>, @kerbowa wrote:
> In D124700#3483633 <https://reviews.llvm.org/D124700#3483633>, @rampitec wrote:
>> In D124700#3483609 <https://reviews.llvm.org/D124700#3483609>, @kerbowa wrote:
>>> In D124700#3483556 <https://reviews.llvm.org/D124700#3483556>, @rampitec wrote:
>>>> You do not handle masks other than 0 yet?
>>> We handle 0 and 1 only.
>> Do you mean 1 is supported simply because it has side effects? If I understand it right you will need to remove this to support more flexible masks, right?
LGTM given that. But change imm to i32 before committing.
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