[PATCH] D124700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

Matt Arsenault via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Fri Apr 29 21:36:25 PDT 2022

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arsenm added a comment.

Can you add a test to make sure the hazard recognizer and code size estimate don’t think this is a real instruction


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124700/new/

https://reviews.llvm.org/D124700

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