[PATCH] D121758: [clang-format] Add support for formatting Verilog code
sstwcw via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Tue Mar 15 16:38:24 PDT 2022
sstwcw added a subscriber: svenvh.
sstwcw added a comment.
Do we have people who use Verilog and knows the clang-format code base? @svenvh Your email address looks like you work for a hardware company. If you know Verilog would you please have a look at this patch?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D121758/new/
https://reviews.llvm.org/D121758
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